From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 28 Apr 2019 19:12:58 +0000 (+0000)
Subject: [X86][SSE] combineExtractVectorElt - add early-out to return zero/undef for out-of... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=1ea33c5f832b127716db188375348183131e31f9;p=llvm

[X86][SSE] combineExtractVectorElt - add early-out to return zero/undef for out-of-range extraction indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359406 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 32e3a80d5c7..c120ec1079f 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -34838,9 +34838,11 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
   SDLoc dl(InputVector);
   bool IsPextr = N->getOpcode() != ISD::EXTRACT_VECTOR_ELT;
 
+  if (CIdx && CIdx->getAPIntValue().uge(SrcVT.getVectorNumElements()))
+    return IsPextr ? DAG.getConstant(0, dl, VT) : DAG.getUNDEF(VT);
+
   // Integer Constant Folding.
-  if (VT.isInteger() && CIdx &&
-      CIdx->getAPIntValue().ult(SrcVT.getVectorNumElements())) {
+  if (CIdx && VT.isInteger()) {
     APInt UndefVecElts;
     SmallVector<APInt, 16> EltBits;
     unsigned VecEltBitWidth = SrcVT.getScalarSizeInBits();