From: Nicolai Haehnle <nhaehnle@gmail.com>
Date: Mon, 24 Apr 2017 16:53:52 +0000 (+0000)
Subject: AMDGPU: Fix crash when scheduling non-memory SMRD instructions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=1c1f7ef631cb3c7af0832ef6d63552a458101177;p=llvm

AMDGPU: Fix crash when scheduling non-memory SMRD instructions

Summary: Fixes piglit spec/arb_shader_clock/execution/*

Reviewers: arsenm

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D32345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301191 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp
index ec8a7f0ad93..d51110bcbd6 100644
--- a/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -138,6 +138,11 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
   }
 
   if (isSMRD(Opc0) && isSMRD(Opc1)) {
+    // Skip time and cache invalidation instructions.
+    if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
+        AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
+      return false;
+
     assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
 
     // Check base reg.
diff --git a/test/CodeGen/AMDGPU/readcyclecounter.ll b/test/CodeGen/AMDGPU/readcyclecounter.ll
index 5c698c839fa..d7b353cd25d 100644
--- a/test/CodeGen/AMDGPU/readcyclecounter.ll
+++ b/test/CodeGen/AMDGPU/readcyclecounter.ll
@@ -22,4 +22,18 @@ define amdgpu_kernel void @test_readcyclecounter(i64 addrspace(1)* %out) #0 {
   ret void
 }
 
+; This test used to crash in ScheduleDAG.
+;
+; GCN-LABEL: {{^}}test_readcyclecounter_smem:
+; SI-DAG: s_memtime
+; VI-DAG: s_memrealtime
+; GCN-DAG: s_load_dword
+define amdgpu_cs i32 @test_readcyclecounter_smem(i64 addrspace(2)* inreg %in) #0 {
+  %cycle0 = call i64 @llvm.readcyclecounter()
+  %in.v = load i64, i64 addrspace(2)* %in
+  %r.64 = add i64 %cycle0, %in.v
+  %r.32 = trunc i64 %r.64 to i32
+  ret i32 %r.32
+}
+
 attributes #0 = { nounwind }