From: Amara Emerson <aemerson@apple.com>
Date: Mon, 2 Sep 2019 08:18:55 +0000 (+0000)
Subject: [AArch64][GlobalISel] Fix zext narrowScalar to use the right type when creating
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=1bf05b092781e049770051688c0d4dff1ee9e364;p=llvm

[AArch64][GlobalISel] Fix zext narrowScalar to use the right type when creating
the merges.

Fixes PR43171.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370627 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c37b115fc91..1fc10a2d11c 100644
--- a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -620,13 +620,15 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
     if (TypeIdx != 0)
       return UnableToLegalize;
 
-    if (SizeOp0 % NarrowTy.getSizeInBits() != 0)
+    LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
+    uint64_t SizeOp1 = SrcTy.getSizeInBits();
+    if (SizeOp0 % SizeOp1 != 0)
       return UnableToLegalize;
 
     // Generate a merge where the bottom bits are taken from the source, and
     // zero everything else.
-    Register ZeroReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
-    unsigned NumParts = SizeOp0 / NarrowTy.getSizeInBits();
+    Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
+    unsigned NumParts = SizeOp0 / SizeOp1;
     SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
     for (unsigned Part = 1; Part < NumParts; ++Part)
       Srcs.push_back(ZeroReg);
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir b/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
index d1001671884..6d4c9698f26 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
@@ -44,6 +44,28 @@ body:             |
     G_STORE %2(s128), %1(p0) :: (store 16)
     RET_ReallyLR
 
+...
+---
+name:            narrow_zext_s128_from_s32
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $w0, $x1
+
+    ; CHECK-LABEL: name: narrow_zext_s128_from_s32
+    ; CHECK: liveins: $w0, $x1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
+    ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
+    ; CHECK: RET_ReallyLR
+    %0:_(s32) = COPY $w0
+    %1:_(p0) = COPY $x1
+    %2:_(s128) = G_ZEXT %0(s32)
+    G_STORE %2(s128), %1(p0) :: (store 16)
+    RET_ReallyLR
+
 ...
 ---
 name:            narrow_zext_s192