From: Craig Topper <craig.topper@intel.com>
Date: Mon, 30 Sep 2019 18:43:27 +0000 (+0000)
Subject: [X86] Address post-commit review from code I accidentally commited in r373136.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=1931c396323f05ee459263b3d83a724c431044cb;p=llvm

[X86] Address post-commit review from code I accidentally commited in r373136.

See https://reviews.llvm.org/D68167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373245 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 18a998dba38..4dc8027d0bd 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -43479,16 +43479,19 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
   // FIXME: We have the (sub Y, (zext (vXi1 X))) -> (add (sext (vXi1 X)), Y) in
   // generic DAG combine without a legal type check, but adding this there
   // caused regressions.
-  if (Subtarget.hasAVX512() && VT.isVector()) {
+  if (VT.isVector()) {
+    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
     if (Op0.getOpcode() == ISD::ZERO_EXTEND &&
-        Op0.getOperand(0).getValueType().getVectorElementType() == MVT::i1) {
+        Op0.getOperand(0).getValueType().getVectorElementType() == MVT::i1 &&
+        TLI.isTypeLegal(Op0.getOperand(0).getValueType())) {
       SDLoc DL(N);
       SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op0.getOperand(0));
       return DAG.getNode(ISD::SUB, DL, VT, Op1, SExt);
     }
 
     if (Op1.getOpcode() == ISD::ZERO_EXTEND &&
-        Op1.getOperand(0).getValueType().getVectorElementType() == MVT::i1) {
+        Op1.getOperand(0).getValueType().getVectorElementType() == MVT::i1 &&
+        TLI.isTypeLegal(Op1.getOperand(0).getValueType())) {
       SDLoc DL(N);
       SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op1.getOperand(0));
       return DAG.getNode(ISD::SUB, DL, VT, Op0, SExt);