From: Craig Topper <craig.topper@gmail.com>
Date: Sat, 18 Feb 2017 21:15:30 +0000 (+0000)
Subject: [X86] Replace XOP vpcmov builtins with native vector logical operations.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=189c9920f80b72883d6f4161aedadbbb1ae8502f;p=clang

[X86] Replace XOP vpcmov builtins with native vector logical operations.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@295570 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/clang/Basic/BuiltinsX86.def b/include/clang/Basic/BuiltinsX86.def
index e147c8fb86..839122c4bb 100644
--- a/include/clang/Basic/BuiltinsX86.def
+++ b/include/clang/Basic/BuiltinsX86.def
@@ -832,8 +832,6 @@ TARGET_BUILTIN(__builtin_ia32_vphaddudq, "V2LLiV4i", "", "xop")
 TARGET_BUILTIN(__builtin_ia32_vphsubbw, "V8sV16c", "", "xop")
 TARGET_BUILTIN(__builtin_ia32_vphsubwd, "V4iV8s", "", "xop")
 TARGET_BUILTIN(__builtin_ia32_vphsubdq, "V2LLiV4i", "", "xop")
-TARGET_BUILTIN(__builtin_ia32_vpcmov, "V2LLiV2LLiV2LLiV2LLi", "", "xop")
-TARGET_BUILTIN(__builtin_ia32_vpcmov_256, "V4LLiV4LLiV4LLiV4LLi", "", "xop")
 TARGET_BUILTIN(__builtin_ia32_vpperm, "V16cV16cV16cV16c", "", "xop")
 TARGET_BUILTIN(__builtin_ia32_vprotb, "V16cV16cV16c", "", "xop")
 TARGET_BUILTIN(__builtin_ia32_vprotw, "V8sV8sV8s", "", "xop")
diff --git a/lib/Headers/xopintrin.h b/lib/Headers/xopintrin.h
index bdf0cec326..6104bc6673 100644
--- a/lib/Headers/xopintrin.h
+++ b/lib/Headers/xopintrin.h
@@ -198,13 +198,13 @@ _mm_hsubq_epi32(__m128i __A)
 static __inline__ __m128i __DEFAULT_FN_ATTRS
 _mm_cmov_si128(__m128i __A, __m128i __B, __m128i __C)
 {
-  return (__m128i)__builtin_ia32_vpcmov((__v2di)__A, (__v2di)__B, (__v2di)__C);
+  return (__m128i)((__v2du)__A & (__v2du)__C) | ((__v2du)__B & ~(__v2du)__C);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS
 _mm256_cmov_si256(__m256i __A, __m256i __B, __m256i __C)
 {
-  return (__m256i)__builtin_ia32_vpcmov_256((__v4di)__A, (__v4di)__B, (__v4di)__C);
+  return (__m256i)((__v4du)__A & (__v4du)__C) | ((__v4du)__B & ~(__v4du)__C);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS
diff --git a/test/CodeGen/xop-builtins.c b/test/CodeGen/xop-builtins.c
index da9a3b925d..5302b9ab8f 100644
--- a/test/CodeGen/xop-builtins.c
+++ b/test/CodeGen/xop-builtins.c
@@ -170,13 +170,19 @@ __m128i test_mm_hsubq_epi32(__m128i a) {
 
 __m128i test_mm_cmov_si128(__m128i a, __m128i b, __m128i c) {
   // CHECK-LABEL: test_mm_cmov_si128
-  // CHECK: call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}})
+  // CHECK: [[AND:%.*]] = and <2 x i64> %{{.*}}, %{{.*}}
+  // CHECK: [[NEG:%.*]] = xor <2 x i64> %{{.*}}, <i64 -1, i64 -1>
+  // CHECK-NEXT: [[ANDN:%.*]] = and <2 x i64> %{{.*}}, [[NEG]]
+  // CHECK-NEXT: %{{.*}} = or <2 x i64> [[AND]], [[ANDN]]
   return _mm_cmov_si128(a, b, c);
 }
 
 __m256i test_mm256_cmov_si256(__m256i a, __m256i b, __m256i c) {
   // CHECK-LABEL: test_mm256_cmov_si256
-  // CHECK: call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %{{.*}}, <4 x i64> %{{.*}}, <4 x i64> %{{.*}})
+  // CHECK: [[AND:%.*]] = and <4 x i64> %{{.*}}, %{{.*}}
+  // CHECK: [[NEG:%.*]] = xor <4 x i64> %{{.*}}, <i64 -1, i64 -1, i64 -1, i64 -1>
+  // CHECK-NEXT: [[ANDN:%.*]] = and <4 x i64> %{{.*}}, [[NEG]]
+  // CHECK-NEXT: %{{.*}} = or <4 x i64> [[AND]], [[ANDN]]
   return _mm256_cmov_si256(a, b, c);
 }