From: Sanjay Patel <spatel@rotateright.com>
Date: Sat, 14 Jan 2017 23:12:29 +0000 (+0000)
Subject: [InstCombine] add test to show missed vector fold; NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=1849414f3e4dd8f340ec902bc244b24738c73a1b;p=llvm

[InstCombine] add test to show missed vector fold; NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292035 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/Transforms/InstCombine/signext.ll b/test/Transforms/InstCombine/signext.ll
index bccadeb396f..66cee2460eb 100644
--- a/test/Transforms/InstCombine/signext.ll
+++ b/test/Transforms/InstCombine/signext.ll
@@ -72,6 +72,19 @@ define i32 @test6(i16 %P) {
   ret i32 %tmp.5
 }
 
+define <2 x i32> @test6_splat_vec(<2 x i12> %P) {
+; CHECK-LABEL: @test6_splat_vec(
+; CHECK-NEXT:    [[Z:%.*]] = zext <2 x i12> %P to <2 x i32>
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw <2 x i32> [[Z]], <i32 20, i32 20>
+; CHECK-NEXT:    [[ASHR:%.*]] = ashr <2 x i32> [[SHL]], <i32 20, i32 20>
+; CHECK-NEXT:    ret <2 x i32> [[ASHR]]
+;
+  %z = zext <2 x i12> %P to <2 x i32>
+  %shl = shl <2 x i32> %z, <i32 20, i32 20>
+  %ashr = ashr <2 x i32> %shl, <i32 20, i32 20>
+  ret <2 x i32> %ashr
+}
+
 define i32 @test7(i32 %x) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:    [[SUB:%.*]] = ashr i32 %x, 5