From: Matt Arsenault Date: Fri, 8 Feb 2019 19:18:01 +0000 (+0000) Subject: AMDGPU: Remove GCN features and predicates X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=163f2c349f4b8bf25b47c76c2fcf39899e8f8004;p=llvm AMDGPU: Remove GCN features and predicates These are no longer necessary since the R600 tablegen files are split out now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353548 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AMDGPU/AMDGPU.td b/lib/Target/AMDGPU/AMDGPU.td index 7b5cbeee54b..761668be11c 100644 --- a/lib/Target/AMDGPU/AMDGPU.td +++ b/lib/Target/AMDGPU/AMDGPU.td @@ -424,31 +424,25 @@ def FeatureDisable : SubtargetFeature<"", "Dummy feature to disable assembler instructions" >; -def FeatureGCN : SubtargetFeature<"gcn", - "IsGCN", - "true", - "GCN or newer GPU" ->; - class GCNSubtargetFeatureGeneration Implies> : SubtargetFeatureGeneration ; def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128, - FeatureWavefrontSize64, FeatureGCN, + FeatureWavefrontSize64, FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange] >; def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, - FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace, + FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange] >; def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, - FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN, + FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts, FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel, FeatureScalarStores, FeatureInv2PiInlineImm, @@ -459,7 +453,7 @@ def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9", [FeatureFP64, FeatureLocalMemorySize65536, - FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN, + FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts, FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm, FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode, diff --git a/lib/Target/AMDGPU/AMDGPUInstructions.td b/lib/Target/AMDGPU/AMDGPUInstructions.td index c44c2faaa0d..bdbfdaf1dc1 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -65,12 +65,8 @@ class ILFormat pattern> def TruePredicate : Predicate<"true">; -// Exists to help track down where SubtargetPredicate isn't set rather -// than letting tablegen crash with an unhelpful error. -def InvalidPred : Predicate<"predicate not set on instruction or pattern">; - class PredicateControl { - Predicate SubtargetPredicate = InvalidPred; + Predicate SubtargetPredicate = TruePredicate; list AssemblerPredicates = []; Predicate AssemblerPredicate = TruePredicate; list OtherPredicates = []; @@ -625,9 +621,7 @@ class Extract_Element { - let SubtargetPredicate = TruePredicate; -} +>; /* Insert element pattern */ class Insert_Element { - let SubtargetPredicate = TruePredicate; -} +>; // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer // can handle COPY instructions. diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 8bd4f3c977f..dda0fe75f80 100644 --- a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -123,6 +123,10 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, HasMovrel = true; } + // Don't crash on invalid devices. + if (WavefrontSize == 0) + WavefrontSize = 64; + HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS; return *this; diff --git a/lib/Target/AMDGPU/DSInstructions.td b/lib/Target/AMDGPU/DSInstructions.td index 7435207ca15..c099a29d1c8 100644 --- a/lib/Target/AMDGPU/DSInstructions.td +++ b/lib/Target/AMDGPU/DSInstructions.td @@ -10,8 +10,6 @@ class DS_Pseudo patt InstSI , SIMCInstr { - let SubtargetPredicate = isGCN; - let LGKM_CNT = 1; let DS = 1; let Size = 8; diff --git a/lib/Target/AMDGPU/GCNProcessors.td b/lib/Target/AMDGPU/GCNProcessors.td index 1aa485c144d..dbd955b568f 100644 --- a/lib/Target/AMDGPU/GCNProcessors.td +++ b/lib/Target/AMDGPU/GCNProcessors.td @@ -9,7 +9,7 @@ // The code produced for "generic" is only useful for tests and cannot // reasonably be expected to execute on any particular target. def : ProcessorModel<"generic", NoSchedModel, - [FeatureGCN, FeatureWavefrontSize64] + [FeatureWavefrontSize64] >; //===----------------------------------------------------------------------===// diff --git a/lib/Target/AMDGPU/MIMGInstructions.td b/lib/Target/AMDGPU/MIMGInstructions.td index 4bf86144fd0..4071adcf200 100644 --- a/lib/Target/AMDGPU/MIMGInstructions.td +++ b/lib/Target/AMDGPU/MIMGInstructions.td @@ -101,7 +101,6 @@ class MIMG let UseNamedOperandTable = 1; let hasSideEffects = 0; // XXX ???? - let SubtargetPredicate = isGCN; let DecoderNamespace = dns; let isAsmParserOnly = !if(!eq(dns,""), 1, 0); let AsmMatchConverter = "cvtMIMG"; diff --git a/lib/Target/AMDGPU/SIInstrFormats.td b/lib/Target/AMDGPU/SIInstrFormats.td index 4824f67aefd..06503ac7dcb 100644 --- a/lib/Target/AMDGPU/SIInstrFormats.td +++ b/lib/Target/AMDGPU/SIInstrFormats.td @@ -10,9 +10,6 @@ // //===----------------------------------------------------------------------===// -def isGCN : Predicate<"Subtarget->getGeneration() " - ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">, - AssemblerPredicate<"FeatureGCN">; def isSI : Predicate<"Subtarget->getGeneration() " "== AMDGPUSubtarget::SOUTHERN_ISLANDS">, AssemblerPredicate<"FeatureSouthernIslands">; @@ -21,8 +18,6 @@ def isSI : Predicate<"Subtarget->getGeneration() " class InstSI pattern = []> : AMDGPUInst, GCNPredicateControl { - let SubtargetPredicate = isGCN; - // Low bits - basic encoding information. field bit SALU = 0; field bit VALU = 0; diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td index 9b99d1bc3ff..88acebb8969 100644 --- a/lib/Target/AMDGPU/SIInstructions.td +++ b/lib/Target/AMDGPU/SIInstructions.td @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// class GCNPat : Pat, GCNPredicateControl { - let SubtargetPredicate = isGCN; + } include "SOPInstructions.td" @@ -581,7 +581,7 @@ def : Pat < // VOP1 Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in { +let OtherPredicates = [UnsafeFPMath] in { //def : RcpPat; //defm : RsqPat; @@ -604,7 +604,7 @@ def : GCNPat < (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE) >; -} // End SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] +} // End OtherPredicates = [UnsafeFPMath] // f16_to_fp patterns @@ -807,8 +807,6 @@ def : Pat < (v2f16 (EXTRACT_SUBREG v4f16:$vec, sub1)) >; -let SubtargetPredicate = isGCN in { - // FIXME: Why do only some of these type combinations for SReg and // VReg? // 16-bit bitcast @@ -891,8 +889,6 @@ def : BitConvert ; def : BitConvert ; def : BitConvert ; -} // End SubtargetPredicate = isGCN - /********** =================== **********/ /********** Src & Dst modifiers **********/ /********** =================== **********/ @@ -1104,9 +1100,7 @@ def : GCNPat < /********** Intrinsic Patterns **********/ /********** ================== **********/ -let SubtargetPredicate = isGCN in { def : POW_Common ; -} def : GCNPat < (i32 (sext i1:$src0)), @@ -1133,8 +1127,6 @@ def : GCNPat < // VOP3 Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN in { - def : IMad24Pat; def : UMad24Pat; @@ -1142,8 +1134,6 @@ def : UMad24Pat; defm : BFIPatterns ; def : ROTRPattern ; -} - def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))), (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)), (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>; @@ -1611,8 +1601,6 @@ multiclass BFMPatterns { >; } -let SubtargetPredicate = isGCN in { - defm : BFMPatterns ; // FIXME: defm : BFMPatterns ; @@ -1622,8 +1610,6 @@ defm : SHA256MaPattern ; defm : IntMed3Pat; defm : IntMed3Pat; -} - // This matches 16 permutations of // max(min(x, y), min(max(x, y), z)) class FPMed3Pat patt let hasSideEffects = 0; let UseNamedOperandTable = 1; let SchedRW = [WriteSMEM]; - let SubtargetPredicate = isGCN; string Mnemonic = opName; string AsmOperands = asmOps; diff --git a/lib/Target/AMDGPU/SOPInstructions.td b/lib/Target/AMDGPU/SOPInstructions.td index bd5120c2b2a..1cb9f27dd02 100644 --- a/lib/Target/AMDGPU/SOPInstructions.td +++ b/lib/Target/AMDGPU/SOPInstructions.td @@ -25,7 +25,6 @@ class SOP_Pseudo { let isPseudo = 1; let isCodeGenOnly = 1; - let SubtargetPredicate = isGCN; let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -757,7 +755,6 @@ class SOPC op, dag outs, dag ins, string asm, let Defs = [SCC]; let SchedRW = [WriteSALU]; let UseNamedOperandTable = 1; - let SubtargetPredicate = isGCN; } class SOPC_Base op, RegisterOperand rc0, RegisterOperand rc1, @@ -855,7 +852,6 @@ class SOPP op, dag ins, string asm, list pattern = []> : let SchedRW = [WriteSALU]; let UseNamedOperandTable = 1; - let SubtargetPredicate = isGCN; } diff --git a/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 8fcac3fdb69..e1727338599 100644 --- a/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -229,7 +229,8 @@ unsigned getEUsPerCU(const MCSubtargetInfo *STI) { unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) { - if (!STI->getFeatureBits().test(FeatureGCN)) + assert(FlatWorkGroupSize != 0); + if (STI->getTargetTriple().getArch() != Triple::amdgcn) return 8; unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize); if (N == 1) diff --git a/lib/Target/AMDGPU/VOP1Instructions.td b/lib/Target/AMDGPU/VOP1Instructions.td index 81dfa23c93b..15006155d9b 100644 --- a/lib/Target/AMDGPU/VOP1Instructions.td +++ b/lib/Target/AMDGPU/VOP1Instructions.td @@ -47,7 +47,6 @@ class VOP1_Pseudo pattern=[], bit VOP1On let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; let VOP1 = 1; let VALU = 1; @@ -155,7 +154,6 @@ def V_READFIRSTLANE_B32 : let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; let VOP1 = 1; let VALU = 1; diff --git a/lib/Target/AMDGPU/VOP2Instructions.td b/lib/Target/AMDGPU/VOP2Instructions.td index 4af96d0a27b..ee165515ce7 100644 --- a/lib/Target/AMDGPU/VOP2Instructions.td +++ b/lib/Target/AMDGPU/VOP2Instructions.td @@ -68,7 +68,6 @@ class VOP2_Pseudo pattern=[], string suf let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; let VOP2 = 1; let VALU = 1; @@ -392,8 +391,6 @@ def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { // VOP2 Instructions //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN, Predicates = [isGCN] in { - defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>; def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; @@ -471,7 +468,6 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT, AMDGPUpk_u16_u32>; defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT, AMDGPUpk_i16_i32>; -} // End SubtargetPredicate = isGCN, Predicates = [isGCN] def : GCNPat< (AMDGPUadde i32:$src0, i32:$src1, i1:$src2), diff --git a/lib/Target/AMDGPU/VOPCInstructions.td b/lib/Target/AMDGPU/VOPCInstructions.td index a8433f54d24..9d610610855 100644 --- a/lib/Target/AMDGPU/VOPCInstructions.td +++ b/lib/Target/AMDGPU/VOPCInstructions.td @@ -82,8 +82,6 @@ class VOPC_Pseudo pattern=[]> : let Uses = [EXEC]; let Defs = [VCC]; - let SubtargetPredicate = isGCN; - VOPProfile Pfl = P; } diff --git a/lib/Target/AMDGPU/VOPInstructions.td b/lib/Target/AMDGPU/VOPInstructions.td index 49df51f6111..e056196c572 100644 --- a/lib/Target/AMDGPU/VOPInstructions.td +++ b/lib/Target/AMDGPU/VOPInstructions.td @@ -99,7 +99,6 @@ class VOP3_Pseudo pattern = [], let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; // Because SGPRs may be allowed if there are multiple operands, we // need a post-isel hook to insert copies in order to avoid diff --git a/test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll b/test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll index 609dc0400c4..44b4d19dbb1 100644 --- a/test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll +++ b/test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s ; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s -; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx800 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s +; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s ; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s ; FUNC-LABEL: {{^}}system_acquire: