From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Wed, 15 Jun 2016 21:05:04 +0000 (+0000)
Subject: [Hexagon] Fix/simplify some conditional statements
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=16185a2b7f50dc24a55bbea7afc5ad8bd3050a0a;p=llvm

[Hexagon] Fix/simplify some conditional statements

Fix for PR28138.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272836 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 4034b69c2a6..96b1397c9db 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1530,7 +1530,7 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
   unsigned SizeA = 0, SizeB = 0;
 
   if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
-      MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
+      MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
     return false;
 
   // Instructions that are pure loads, not loads and stores like memops are not
@@ -3673,8 +3673,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
   case Hexagon::S4_storeirb_io:
     // memb(Rs+#u4) = #U1
     Src1Reg = MI->getOperand(0).getReg();
-    if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
-        isUInt<4>(MI->getOperand(1).getImm()) && MI->getOperand(2).isImm() &&
+    if (isIntRegForSubInst(Src1Reg) &&
+        MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()) &&
         MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
       return HexagonII::HSIG_S2;
     break;