From: Craig Topper <craig.topper@intel.com>
Date: Sun, 10 Dec 2017 09:14:39 +0000 (+0000)
Subject: [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=15efc6e596f412a4385f20d60390d55ffd78e2b7;p=llvm

[X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320291 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86SchedBroadwell.td b/lib/Target/X86/X86SchedBroadwell.td
index 429afccbe92..1492f9fd6f9 100755
--- a/lib/Target/X86/X86SchedBroadwell.td
+++ b/lib/Target/X86/X86SchedBroadwell.td
@@ -590,7 +590,7 @@ def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup6], (instregex "ADCX32rr")>;
@@ -663,7 +663,7 @@ def: InstRW<[BWWriteResGroup6], (instregex "SAR8r1")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SAR8ri")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SARX32rr")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SARX64rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SETAEr")>;
@@ -919,12 +919,12 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup9], (instregex "ADD8i8")>;
 def: InstRW<[BWWriteResGroup9], (instregex "ADD8ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup9], (instregex "AND8i8")>;
 def: InstRW<[BWWriteResGroup9], (instregex "AND8ri")>;
@@ -932,7 +932,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "AND8rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CBW")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CLC")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CMC")>;
-def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CMP8i8")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CMP8ri")>;
@@ -956,7 +956,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "NEG8r")>;
 def: InstRW<[BWWriteResGroup9], (instregex "NOOP")>;
 def: InstRW<[BWWriteResGroup9], (instregex "NOT(16|32|64)r")>;
 def: InstRW<[BWWriteResGroup9], (instregex "NOT8r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup9], (instregex "OR8i8")>;
 def: InstRW<[BWWriteResGroup9], (instregex "OR8ri")>;
@@ -968,7 +968,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "SLDT64m")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SMSW16m")>;
 def: InstRW<[BWWriteResGroup9], (instregex "STC")>;
 def: InstRW<[BWWriteResGroup9], (instregex "STRm")>;
-def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SUB8i8")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SUB8ri")>;
@@ -979,7 +979,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
 def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "TEST8rr")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)rr(_REV)?")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XOR8i8")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XOR8ri")>;
@@ -2374,7 +2374,7 @@ def: InstRW<[BWWriteResGroup66], (instregex "ADD(16|32|64)rm")>;
 def: InstRW<[BWWriteResGroup66], (instregex "ADD8rm")>;
 def: InstRW<[BWWriteResGroup66], (instregex "AND(16|32|64)rm")>;
 def: InstRW<[BWWriteResGroup66], (instregex "AND8rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mr")>;
 def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)rm")>;
 def: InstRW<[BWWriteResGroup66], (instregex "CMP8mi")>;
@@ -2432,11 +2432,11 @@ def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
-def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
 def: InstRW<[BWWriteResGroup70], (instregex "ADD8mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "ADD8mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mr")>;
 def: InstRW<[BWWriteResGroup70], (instregex "AND8mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "AND8mr")>;
@@ -2448,17 +2448,17 @@ def: InstRW<[BWWriteResGroup70], (instregex "NEG(16|32|64)m")>;
 def: InstRW<[BWWriteResGroup70], (instregex "NEG8m")>;
 def: InstRW<[BWWriteResGroup70], (instregex "NOT(16|32|64)m")>;
 def: InstRW<[BWWriteResGroup70], (instregex "NOT8m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mr")>;
 def: InstRW<[BWWriteResGroup70], (instregex "OR8mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "OR8mr")>;
 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm")>;
 def: InstRW<[BWWriteResGroup70], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
 def: InstRW<[BWWriteResGroup70], (instregex "SUB8mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "SUB8mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
 def: InstRW<[BWWriteResGroup70], (instregex "XOR8mi")>;
 def: InstRW<[BWWriteResGroup70], (instregex "XOR8mr")>;
@@ -2958,7 +2958,7 @@ def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
   let NumMicroOps = 6;
   let ResourceCycles = [1,1,1,3];
 }
-def: InstRW<[BWWriteResGroup99], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup99], (instregex "ADC(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup99], (instregex "ADC8mi")>;
 def: InstRW<[BWWriteResGroup99], (instregex "ADD8mi")>;
 def: InstRW<[BWWriteResGroup99], (instregex "AND8mi")>;
@@ -2981,7 +2981,7 @@ def: InstRW<[BWWriteResGroup100], (instregex "ROL(16|32|64)mCL")>;
 def: InstRW<[BWWriteResGroup100], (instregex "ROL8mCL")>;
 def: InstRW<[BWWriteResGroup100], (instregex "SAR(16|32|64)mCL")>;
 def: InstRW<[BWWriteResGroup100], (instregex "SAR8mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mi")>;
 def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mr")>;
 def: InstRW<[BWWriteResGroup100], (instregex "SBB8mi")>;
 def: InstRW<[BWWriteResGroup100], (instregex "SBB8mr")>;
diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td
index b1221fc1498..5665470fd8d 100644
--- a/lib/Target/X86/X86SchedHaswell.td
+++ b/lib/Target/X86/X86SchedHaswell.td
@@ -1463,12 +1463,12 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
@@ -1476,7 +1476,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "AND8rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
-def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
@@ -1500,7 +1500,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
 def: InstRW<[HWWriteResGroup10], (instregex "NOT(16|32|64)r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
-def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
@@ -1512,7 +1512,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "SLDT64m")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
 def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
 def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
-def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
@@ -1523,7 +1523,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;
@@ -2077,7 +2077,7 @@ def: InstRW<[HWWriteResGroup18], (instregex "ADD(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "ADD8rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "AND(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "AND8rm")>;
-def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP8mi")>;
@@ -2198,11 +2198,11 @@ def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
-def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "ADD8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "ADD8mr")>;
-def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "AND8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "AND8mr")>;
@@ -2214,17 +2214,17 @@ def: InstRW<[HWWriteResGroup26], (instregex "NEG(16|32|64)m")>;
 def: InstRW<[HWWriteResGroup26], (instregex "NEG8m")>;
 def: InstRW<[HWWriteResGroup26], (instregex "NOT(16|32|64)m")>;
 def: InstRW<[HWWriteResGroup26], (instregex "NOT8m")>;
-def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "OR8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "OR8mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm")>;
 def: InstRW<[HWWriteResGroup26], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "SUB8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "SUB8mr")>;
-def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "XOR8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "XOR8mr")>;
@@ -2355,7 +2355,7 @@ def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC8ri")>;
@@ -2376,7 +2376,7 @@ def: InstRW<[HWWriteResGroup35], (instregex "CMOVP(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup35], (instregex "CMOVS(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup35], (instregex "CWD")>;
 def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
-def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB8ri")>;
@@ -3033,7 +3033,7 @@ def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
   let NumMicroOps = 6;
   let ResourceCycles = [1,1,1,3];
 }
-def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup68], (instregex "ADC8mi")>;
 def: InstRW<[HWWriteResGroup68], (instregex "ADD8mi")>;
 def: InstRW<[HWWriteResGroup68], (instregex "AND8mi")>;
@@ -3056,7 +3056,7 @@ def: InstRW<[HWWriteResGroup69], (instregex "ROL(16|32|64)mCL")>;
 def: InstRW<[HWWriteResGroup69], (instregex "ROL8mCL")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SAR(16|32|64)mCL")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SAR8mCL")>;
-def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SBB8mi")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SBB8mr")>;
diff --git a/lib/Target/X86/X86SchedSandyBridge.td b/lib/Target/X86/X86SchedSandyBridge.td
index cacd5955c8f..dfebd3ae124 100644
--- a/lib/Target/X86/X86SchedSandyBridge.td
+++ b/lib/Target/X86/X86SchedSandyBridge.td
@@ -691,19 +691,19 @@ def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "ADD8i8")>;
 def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "AND8i8")>;
 def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CBW")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CMC")>;
-def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CMP8i8")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>;
@@ -730,7 +730,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "NEG(16|32|64)r")>;
 def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>;
 def: InstRW<[SBWriteResGroup6], (instregex "NOT(16|32|64)r")>;
 def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>;
-def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "OR8i8")>;
 def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>;
@@ -740,7 +740,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "STC")>;
-def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "SUB8i8")>;
 def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>;
@@ -755,7 +755,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "XOR8i8")>;
 def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>;
@@ -903,7 +903,7 @@ def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> {
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup19], (instregex "ADC8ri")>;
 def: InstRW<[SBWriteResGroup19], (instregex "ADC8rr")>;
@@ -921,7 +921,7 @@ def: InstRW<[SBWriteResGroup19], (instregex "CMOVNS(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup19], (instregex "CMOVO(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup19], (instregex "CMOVP(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup19], (instregex "CMOVS(16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup19], (instregex "SBB8ri")>;
 def: InstRW<[SBWriteResGroup19], (instregex "SBB8rr")>;
@@ -1584,7 +1584,7 @@ def: InstRW<[SBWriteResGroup52], (instregex "ADD(16|32|64)rm")>;
 def: InstRW<[SBWriteResGroup52], (instregex "ADD8rm")>;
 def: InstRW<[SBWriteResGroup52], (instregex "AND(16|32|64)rm")>;
 def: InstRW<[SBWriteResGroup52], (instregex "AND8rm")>;
-def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)rm")>;
 def: InstRW<[SBWriteResGroup52], (instregex "CMP8mi")>;
@@ -1989,11 +1989,11 @@ def SBWriteResGroup70 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
   let NumMicroOps = 4;
   let ResourceCycles = [1,2,1];
 }
-def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "AND8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "AND8mr")>;
@@ -2005,18 +2005,18 @@ def: InstRW<[SBWriteResGroup70], (instregex "NEG(16|32|64)m")>;
 def: InstRW<[SBWriteResGroup70], (instregex "NEG8m")>;
 def: InstRW<[SBWriteResGroup70], (instregex "NOT(16|32|64)m")>;
 def: InstRW<[SBWriteResGroup70], (instregex "NOT8m")>;
-def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>;
@@ -2423,9 +2423,9 @@ def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
   let NumMicroOps = 6;
   let ResourceCycles = [1,2,3];
 }
-def: InstRW<[SBWriteResGroup98], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup98], (instregex "ADC(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup98], (instregex "ADC8mi")>;
-def: InstRW<[SBWriteResGroup98], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SBWriteResGroup98], (instregex "SBB(16|32|64)mi")>;
 def: InstRW<[SBWriteResGroup98], (instregex "SBB8mi")>;
 
 def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
diff --git a/lib/Target/X86/X86SchedSkylakeClient.td b/lib/Target/X86/X86SchedSkylakeClient.td
index db6b605fa69..ee10db31c07 100644
--- a/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/lib/Target/X86/X86SchedSkylakeClient.td
@@ -701,7 +701,7 @@ def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "ADCX32rr")>;
@@ -775,7 +775,7 @@ def: InstRW<[SKLWriteResGroup7], (instregex "SAR8r1")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SAR8ri")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SARX32rr")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SARX64rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SETAEr")>;
@@ -920,12 +920,12 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "ADD8i8")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "ADD8ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "AND8i8")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "AND8ri")>;
@@ -933,7 +933,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "AND8rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CBW")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CLC")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CMC")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CMP8i8")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CMP8ri")>;
@@ -957,7 +957,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "NEG8r")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "NOOP")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "NOT(16|32|64)r")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "NOT8r")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "OR8i8")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "OR8ri")>;
@@ -969,7 +969,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "SLDT64m")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SMSW16m")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "STC")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "STRm")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SUB8i8")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SUB8ri")>;
@@ -980,7 +980,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "TEST8rr")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XOR8i8")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XOR8ri")>;
@@ -2222,7 +2222,7 @@ def: InstRW<[SKLWriteResGroup76], (instregex "ADD(16|32|64)rm")>;
 def: InstRW<[SKLWriteResGroup76], (instregex "ADD8rm")>;
 def: InstRW<[SKLWriteResGroup76], (instregex "AND(16|32|64)rm")>;
 def: InstRW<[SKLWriteResGroup76], (instregex "AND8rm")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)rm")>;
 def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mi")>;
@@ -2313,11 +2313,11 @@ def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort015
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
-def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mr")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "AND8mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "AND8mr")>;
@@ -2329,17 +2329,17 @@ def: InstRW<[SKLWriteResGroup83], (instregex "NEG(16|32|64)m")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "NEG8m")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "NOT(16|32|64)m")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "NOT8m")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "OR8mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "OR8mr")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mr")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mi")>;
 def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mr")>;
@@ -3019,7 +3019,7 @@ def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort01
   let NumMicroOps = 6;
   let ResourceCycles = [1,1,1,3];
 }
-def: InstRW<[SKLWriteResGroup118], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup118], (instregex "ADC(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup118], (instregex "ADC8mi")>;
 
 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
@@ -3031,7 +3031,7 @@ def: InstRW<[SKLWriteResGroup119], (instregex "ADC(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup119], (instregex "ADC8mr")>;
 def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(16|32|64)rm")>;
 def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG8rm")>;
-def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mi")>;
 def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mi")>;
 def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mr")>;
diff --git a/lib/Target/X86/X86SchedSkylakeServer.td b/lib/Target/X86/X86SchedSkylakeServer.td
index 4843b6d45ea..a86adbd7b7f 100755
--- a/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1004,7 +1004,7 @@ def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "ADCX32rr")>;
@@ -1078,7 +1078,7 @@ def: InstRW<[SKXWriteResGroup7], (instregex "SAR8r1")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SAR8ri")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SARX32rr")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SARX64rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SETAEr")>;
@@ -1349,12 +1349,12 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "ADD8i8")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "ADD8ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "AND8i8")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "AND8ri")>;
@@ -1362,7 +1362,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "AND8rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CBW")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CLC")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CMC")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CMP8i8")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CMP8ri")>;
@@ -1386,7 +1386,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "NEG8r")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "NOOP")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "NOT(16|32|64)r")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "NOT8r")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "OR8i8")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "OR8ri")>;
@@ -1398,7 +1398,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "SLDT64m")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SMSW16m")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "STC")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "STRm")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SUB8i8")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SUB8ri")>;
@@ -1409,7 +1409,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "TEST8rr")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV)?")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XOR8i8")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XOR8ri")>;
@@ -3537,7 +3537,7 @@ def: InstRW<[SKXWriteResGroup81], (instregex "ADD(16|32|64)rm")>;
 def: InstRW<[SKXWriteResGroup81], (instregex "ADD8rm")>;
 def: InstRW<[SKXWriteResGroup81], (instregex "AND(16|32|64)rm")>;
 def: InstRW<[SKXWriteResGroup81], (instregex "AND8rm")>;
-def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)rm")>;
 def: InstRW<[SKXWriteResGroup81], (instregex "CMP8mi")>;
@@ -3624,11 +3624,11 @@ def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort015
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
-def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "ADD8mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "ADD8mr")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "AND8mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "AND8mr")>;
@@ -3640,17 +3640,17 @@ def: InstRW<[SKXWriteResGroup87], (instregex "NEG(16|32|64)m")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "NEG8m")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "NOT(16|32|64)m")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "NOT8m")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "OR8mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "OR8mr")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "SUB8mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "SUB8mr")>;
-def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "XOR8mi")>;
 def: InstRW<[SKXWriteResGroup87], (instregex "XOR8mr")>;
@@ -4915,7 +4915,7 @@ def SKXWriteResGroup129 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort01
   let NumMicroOps = 6;
   let ResourceCycles = [1,1,1,3];
 }
-def: InstRW<[SKXWriteResGroup129], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup129], (instregex "ADC(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup129], (instregex "ADC8mi")>;
 
 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
@@ -4927,7 +4927,7 @@ def: InstRW<[SKXWriteResGroup130], (instregex "ADC(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup130], (instregex "ADC8mr")>;
 def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(16|32|64)rm")>;
 def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG8rm")>;
-def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mi")>;
 def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mr")>;
 def: InstRW<[SKXWriteResGroup130], (instregex "SBB8mi")>;
 def: InstRW<[SKXWriteResGroup130], (instregex "SBB8mr")>;