From: Ahmed Bougacha Date: Fri, 21 Aug 2015 23:34:20 +0000 (+0000) Subject: [ARM NEON] Use the common naming scheme for vcvt f16 builtins. NFC. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=1547b6ad9bcccff224a2d8e863f9425bfdbdfe83;p=clang [ARM NEON] Use the common naming scheme for vcvt f16 builtins. NFC. We had "vcvt_f16" and "VCVT_HIGH_F16": for other FP types, this naming is used for intrinsics with integer overloads. The FP->FP conversions, on the other hand, use the full "vcvt_f32_f64" name instead. Use the same naming convention for the f16<->f32 conversions. While there, reorder the definitions a little bit. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@245763 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td index c6f879513e..6e29cb21dc 100644 --- a/include/clang/Basic/arm_neon.td +++ b/include/clang/Basic/arm_neon.td @@ -414,7 +414,7 @@ def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>; def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0), (call "vqmovun", $p1))>; def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>; -def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16", $p1))>; +def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16_f32", $p1))>; def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>; def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>; def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>; @@ -687,16 +687,19 @@ def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; //////////////////////////////////////////////////////////////////////////////// // E.3.22 Converting vectors + +def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "hk", "f">; +def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">; + def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; -def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">; def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; -def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">; let isVCVT_N = 1 in { def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; } + def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; @@ -923,6 +926,9 @@ def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">; // Reciprocal/Sqrt def FRECPS : IInst<"vrecps", "ddd", "dQd">; def FRSQRTS : IInst<"vrsqrts", "ddd", "dQd">; +def FRECPE : SInst<"vrecpe", "dd", "dQd">; +def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">; +def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">; //////////////////////////////////////////////////////////////////////////////// // bitwise reverse @@ -942,20 +948,21 @@ def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>; //////////////////////////////////////////////////////////////////////////////// // Converting vectors -def VCVT_HIGH_F16 : SOpInst<"vcvt_high_f16", "qhj", "f", OP_VCVT_NA_HI_F16>; -def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI_F32>; + def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "md", "Qd">; -def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI_F32>; def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">; + +def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">; +def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">; def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">; + +def VCVT_HIGH_F16_f32 : SOpInst<"vcvt_high_f16", "qhj", "f", OP_VCVT_NA_HI_F16>; +def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI_F32>; +def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI_F32>; def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI_F64>; -def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">; + +def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">; def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>; -def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">; -def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">; -def FRECPE : SInst<"vrecpe", "dd", "dQd">; -def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">; -def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">; //////////////////////////////////////////////////////////////////////////////// // Comparison diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp index 394d0d15b1..105e50557f 100644 --- a/lib/CodeGen/CGBuiltin.cpp +++ b/lib/CodeGen/CGBuiltin.cpp @@ -2102,7 +2102,7 @@ static NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = { NEONMAP1(vclzq_v, ctlz, Add1ArgType), NEONMAP1(vcnt_v, ctpop, Add1ArgType), NEONMAP1(vcntq_v, ctpop, Add1ArgType), - NEONMAP1(vcvt_f16_v, arm_neon_vcvtfp2hf, 0), + NEONMAP1(vcvt_f16_f32, arm_neon_vcvtfp2hf, 0), NEONMAP1(vcvt_f32_f16, arm_neon_vcvthf2fp, 0), NEONMAP0(vcvt_f32_v), NEONMAP2(vcvt_n_f32_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0), @@ -2315,7 +2315,7 @@ static NeonIntrinsicInfo AArch64SIMDIntrinsicMap[] = { NEONMAP1(vclzq_v, ctlz, Add1ArgType), NEONMAP1(vcnt_v, ctpop, Add1ArgType), NEONMAP1(vcntq_v, ctpop, Add1ArgType), - NEONMAP1(vcvt_f16_v, aarch64_neon_vcvtfp2hf, 0), + NEONMAP1(vcvt_f16_f32, aarch64_neon_vcvtfp2hf, 0), NEONMAP1(vcvt_f32_f16, aarch64_neon_vcvthf2fp, 0), NEONMAP0(vcvt_f32_v), NEONMAP2(vcvt_n_f32_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0), diff --git a/utils/TableGen/NeonEmitter.cpp b/utils/TableGen/NeonEmitter.cpp index 37fd7f9462..c77e91e02f 100644 --- a/utils/TableGen/NeonEmitter.cpp +++ b/utils/TableGen/NeonEmitter.cpp @@ -1069,8 +1069,8 @@ std::string Intrinsic::mangleName(std::string Name, ClassKind LocalCK) const { std::string typeCode = getInstTypeCode(BaseType, LocalCK); std::string S = Name; - if (Name == "vcvt_f32_f16" || Name == "vcvt_f32_f64" || - Name == "vcvt_f64_f32") + if (Name == "vcvt_f16_f32" || Name == "vcvt_f32_f16" || + Name == "vcvt_f32_f64" || Name == "vcvt_f64_f32") return Name; if (typeCode.size() > 0) {