From: Benjamin Kramer Date: Sun, 12 Jun 2016 17:30:47 +0000 (+0000) Subject: Run clang-tidy's performance-unnecessary-copy-initialization over LLVM. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=13c42d2b20388e95b86efadd1cfeb4f1f93a3acf;p=llvm Run clang-tidy's performance-unnecessary-copy-initialization over LLVM. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272516 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index 51226fd639c..7fba7688f7f 100644 --- a/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -998,7 +998,7 @@ void DwarfDebug::beginInstruction(const MachineInstr *MI) { // Check if source location changes, but ignore DBG_VALUE locations. if (!MI->isDebugValue()) { - DebugLoc DL = MI->getDebugLoc(); + const DebugLoc &DL = MI->getDebugLoc(); if (DL != PrevInstLoc) { if (DL) { unsigned Flags = 0; diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 633d1a47689..67efa206a40 100644 --- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -1139,7 +1139,7 @@ bool HexagonAsmParser::parseOperand(OperandVector &Operands) { static char const *RParen = ")"; Operands.push_back(HexagonOperand::CreateToken(LParen, Begin)); Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); - AsmToken MaybeDotNew = Lexer.getTok(); + const AsmToken &MaybeDotNew = Lexer.getTok(); if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && MaybeDotNew.getString().equals_lower(".new")) splitIdentifier(Operands); @@ -1155,7 +1155,7 @@ bool HexagonAsmParser::parseOperand(OperandVector &Operands) { Operands.insert(Operands.end () - 1, HexagonOperand::CreateToken(LParen, Begin)); Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); - AsmToken MaybeDotNew = Lexer.getTok(); + const AsmToken &MaybeDotNew = Lexer.getTok(); if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && MaybeDotNew.getString().equals_lower(".new")) splitIdentifier(Operands); diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp index a6a9e33dd17..d69554f95f9 100644 --- a/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1302,7 +1302,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B, continue; // If found, replace the instruction with a COPY. - DebugLoc DL = MI->getDebugLoc(); + const DebugLoc &DL = MI->getDebugLoc(); const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); unsigned NewR = MRI.createVirtualRegister(FRC); BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR) diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 27562b03b70..2665acd19fb 100644 --- a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -960,7 +960,7 @@ void HexagonEarlyIfConversion::eliminatePhis(MachineBasicBlock *B) { // MRI.replaceVregUsesWith does not allow to update the subregister, // so instead of doing the use-iteration here, create a copy into a // "non-subregistered" register. - DebugLoc DL = PN->getDebugLoc(); + const DebugLoc &DL = PN->getDebugLoc(); const TargetRegisterClass *RC = MRI->getRegClass(DefR); NewR = MRI->createVirtualRegister(RC); NonPHI = BuildMI(*B, NonPHI, DL, TII->get(TargetOpcode::COPY), NewR) diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp index bf16c128e2f..f3a7887e6bd 100644 --- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -616,7 +616,7 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, bool PredSense, bool ReadUndef, bool ImpUse) { MachineInstr *MI = SrcOp.getParent(); MachineBasicBlock &B = *At->getParent(); - DebugLoc DL = MI->getDebugLoc(); + const DebugLoc &DL = MI->getDebugLoc(); // Don't avoid identity copies here (i.e. if the source and the destination // are the same registers). It is actually better to generate them here, diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index 10742769b8a..92ba475fdb2 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -2120,7 +2120,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, MachineBasicBlock::iterator StartIt = SI, NextIt; MachineInstr *CopyIn = nullptr; if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) { - DebugLoc DL = SI->getDebugLoc(); + const DebugLoc &DL = SI->getDebugLoc(); CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR) .addOperand(SrcOp); } diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 5d5b0a68529..23ebfd484be 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -196,7 +196,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // register and use it with offset 0. auto &MRI = MF.getRegInfo(); unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); - DebugLoc DL = MI.getDebugLoc(); + const DebugLoc &DL = MI.getDebugLoc(); BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR) .addReg(BP) .addImm(RealOffset); diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index a50c92a3e44..75c36add77a 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -1191,7 +1191,7 @@ MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, unsigned SrcReg) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + const DebugLoc &DL = MI->getDebugLoc(); if (Subtarget.hasMips32r2() && Size == 1) { BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index 3954ee72c11..4d71d20ac78 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1830,7 +1830,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; MachineInstr *MI = I; - DebugLoc dl = MI->getDebugLoc(); + const DebugLoc &dl = MI->getDebugLoc(); if (isInt<16>(CalleeAmt)) { BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 9aafa896e87..e6f15e8af53 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -786,7 +786,7 @@ static const TableEntry PopTable[] = { /// void FPS::popStackAfter(MachineBasicBlock::iterator &I) { MachineInstr* MI = I; - DebugLoc dl = MI->getDebugLoc(); + const DebugLoc &dl = MI->getDebugLoc(); ASSERT_SORTED(PopTable); if (StackTop == 0) report_fatal_error("Cannot pop empty stack!"); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index c890ded2c56..16d33dbd606 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2504,7 +2504,7 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, llvm_unreachable("Unexpected instruction!"); } - DebugLoc DL = Orig->getDebugLoc(); + const DebugLoc &DL = Orig->getDebugLoc(); BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0)) .addImm(Value); } else { diff --git a/lib/Transforms/Utils/InlineFunction.cpp b/lib/Transforms/Utils/InlineFunction.cpp index c8878b0ec0a..40f5d4ce361 100644 --- a/lib/Transforms/Utils/InlineFunction.cpp +++ b/lib/Transforms/Utils/InlineFunction.cpp @@ -1302,7 +1302,7 @@ updateInlinedAtInfo(const DebugLoc &DL, DILocation *InlinedAtNode, /// to encode location where these instructions are inlined. static void fixupLineNumbers(Function *Fn, Function::iterator FI, Instruction *TheCall) { - DebugLoc TheCallDL = TheCall->getDebugLoc(); + const DebugLoc &TheCallDL = TheCall->getDebugLoc(); if (!TheCallDL) return; diff --git a/tools/llvm-mc/llvm-mc.cpp b/tools/llvm-mc/llvm-mc.cpp index aaf88078124..d75e24f1d17 100644 --- a/tools/llvm-mc/llvm-mc.cpp +++ b/tools/llvm-mc/llvm-mc.cpp @@ -250,7 +250,7 @@ static int AsLexInput(SourceMgr &SrcMgr, MCAsmInfo &MAI, bool Error = false; while (Lexer.Lex().isNot(AsmToken::Eof)) { - AsmToken Tok = Lexer.getTok(); + const AsmToken &Tok = Lexer.getTok(); switch (Tok.getKind()) { default: diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index d945651bb0a..395ecc43865 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -576,7 +576,7 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { O << " switch(AltIdx) {\n" << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; for (const Record *R : AltNameIndices) { - std::string AltName(R->getName()); + const std::string &AltName = R->getName(); std::string Prefix = !Namespace.empty() ? Namespace + "::" : ""; O << " case " << Prefix << AltName << ":\n" << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" diff --git a/utils/TableGen/DFAPacketizerEmitter.cpp b/utils/TableGen/DFAPacketizerEmitter.cpp index 0e74a2f29ae..e31caaf3c98 100644 --- a/utils/TableGen/DFAPacketizerEmitter.cpp +++ b/utils/TableGen/DFAPacketizerEmitter.cpp @@ -709,7 +709,7 @@ int DFAPacketizerEmitter::collectAllComboFuncs( Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc"); const std::vector &FuncList = FuncData->getValueAsListOfDefs("FuncList"); - std::string ComboFuncName = ComboFunc->getName(); + const std::string &ComboFuncName = ComboFunc->getName(); unsigned ComboBit = FUNameToBitsMap[ComboFuncName]; unsigned ComboResources = ComboBit; DEBUG(dbgs() << " combo: " << ComboFuncName