From: Chen Zheng <czhengsz@cn.ibm.com>
Date: Tue, 21 May 2019 05:06:09 +0000 (+0000)
Subject: [PowerPC] test cases for selecting x-form instruction for unaligned offset - NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=131d9404014aa8033040a9aafd9dc19e24dd8086;p=llvm

[PowerPC] test cases for selecting x-form instruction for unaligned offset - NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361219 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/PowerPC/unaligned-addressing-mode.ll b/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
new file mode 100644
index 00000000000..a2732f4626a
--- /dev/null
+++ b/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s
+
+; ISEL matches address mode xaddr.
+define i8 @test_xaddr(i8* %p) {
+; CHECK-LABEL: test_xaddr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    ori r4, r4, 40000
+; CHECK-NEXT:    std r3, -8(r1)
+; CHECK-NEXT:    lbzx r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %p.addr = alloca i8*, align 8
+  store i8* %p, i8** %p.addr, align 8
+  %0 = load i8*, i8** %p.addr, align 8
+  %add.ptr = getelementptr inbounds i8, i8* %0, i64 40000
+  %1 = load i8, i8* %add.ptr, align 1
+  ret i8 %1
+}
+
+; ISEL matches address mode xaddrX4.
+define i64 @test_xaddrX4(i8* %p) {
+; CHECK-LABEL: test_xaddrX4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    std r3, -8(r1)
+; CHECK-NEXT:    addi r3, r3, 3
+; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  %p.addr = alloca i8*, align 8
+  store i8* %p, i8** %p.addr, align 8
+  %0 = load i8*, i8** %p.addr, align 8
+  %add.ptr = getelementptr inbounds i8, i8* %0, i64 3
+  %1 = bitcast i8* %add.ptr to i64*
+  %2 = load i64, i64* %1, align 8
+  ret i64 %2
+}
+
+; ISEL matches address mode xaddrX16.
+define <2 x double> @test_xaddrX16(double* %arr) {
+; CHECK-LABEL: test_xaddrX16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r3, r3, 40
+; CHECK-NEXT:    lxvx vs34, 0, r3
+; CHECK-NEXT:    blr
+entry:
+  %arrayidx1 = getelementptr inbounds double, double* %arr, i64 5
+  %0 = bitcast double* %arrayidx1 to <2 x double>*
+  %1 = load <2 x double>, <2 x double>* %0, align 16
+  ret <2 x double> %1
+}
+
+; ISEL matches address mode xoaddr.
+define void @test_xoaddr(i32* %arr, i32* %arrTo) {
+; CHECK-LABEL: test_xoaddr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r3, r3, 8
+; CHECK-NEXT:    lxvx vs0, 0, r3
+; CHECK-NEXT:    addi r4, r4, 4
+; CHECK-NEXT:    stxvx vs0, 0, r4
+; CHECK-NEXT:    blr
+entry:
+  %arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
+  %0 = bitcast i32* %arrayidx to <4 x i32>*
+  %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
+  %1 = bitcast i32* %arrayidx1 to <4 x i32>*
+  %2 = load <4 x i32>, <4 x i32>* %1, align 8
+  store <4 x i32> %2, <4 x i32>* %0, align 8
+  ret void
+}
+
+; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
+; loop.
+define i64 @test_xaddrX4_loop(i8* %p) {
+; CHECK-LABEL: test_xaddrX4_loop:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r4, r3, -8
+; CHECK-NEXT:    li r3, 8
+; CHECK-NEXT:    mtctr r3
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB4_1: # %for.body
+; CHECK:         ldu r5, 8(r4)
+; CHECK-NEXT:    addi r6, r4, 3
+; CHECK-NEXT:    ld r6, 0(r6)
+; CHECK-NEXT:    maddld r3, r6, r5, r3
+; CHECK-NEXT:    bdnz .LBB4_1
+; CHECK-NEXT:  # %bb.2: # %for.end
+; CHECK-NEXT:    blr
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.015 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
+  %res.014 = phi i64 [ 0, %entry ], [ %add, %for.body ]
+  %mul = shl i64 %i.015, 3
+  %add.ptr = getelementptr inbounds i8, i8* %p, i64 %mul
+  %0 = bitcast i8* %add.ptr to i64*
+  %1 = load i64, i64* %0, align 8
+  %add.ptr3 = getelementptr inbounds i8, i8* %add.ptr, i64 3
+  %2 = bitcast i8* %add.ptr3 to i64*
+  %3 = load i64, i64* %2, align 8
+  %mul4 = mul i64 %3, %1
+  %add = add i64 %mul4, %res.014
+  %inc = add nuw nsw i64 %i.015, 1
+  %exitcond = icmp eq i64 %inc, 8
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i64 %add
+
+}