From: Kai Luo <lkail@cn.ibm.com>
Date: Fri, 2 Aug 2019 03:14:17 +0000 (+0000)
Subject: [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=122b03d24699e6998a4c88a8f4b46fd7f81d8769;p=llvm

[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register

Summary:
When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check
if `extsw`'s second operand is a virtual register, otherwise we might
get miscompile.

Differential Revision: https://reviews.llvm.org/D65315

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367645 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCMIPeephole.cpp b/lib/Target/PowerPC/PPCMIPeephole.cpp
index 1b48bbaf1f4..fe4f351e639 100644
--- a/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -1426,6 +1426,12 @@ bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
   if (!MRI->hasOneNonDBGUse(SrcReg))
     return false;
 
+  assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
+  assert(SrcMI->getOperand(1).isReg() &&
+         "EXTSW's second operand should be a register");
+  if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+    return false;
+
   LLVM_DEBUG(dbgs() << "Combining pair: ");
   LLVM_DEBUG(SrcMI->dump());
   LLVM_DEBUG(MI.dump());
diff --git a/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir b/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
index 5c78e408ffc..76fde05be70 100644
--- a/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
+++ b/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
@@ -20,10 +20,11 @@ body:             |
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   liveins: $x3
+  ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
   ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
   ; CHECK:   $x3 = COPY [[RLDICR]]
-  ; CHECK:   [[EXTSWSLI:%[0-9]+]]:g8rc = EXTSWSLI $x3, 2, implicit-def $carry
-  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[EXTSWSLI]]
+  ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
+  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
   ; CHECK:   $x3 = COPY [[ADD8_]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   ; CHECK: bb.2: