From: Jessica Paquette Date: Wed, 3 Jul 2019 17:46:23 +0000 (+0000) Subject: [GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=11cb153503d777c4bf39816761e6cedaf19c1369;p=llvm [GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed Instead of just stopping to see if we have a G_CONSTANT, instead, look through G_TRUNCs, G_SEXTs, and G_ZEXTs. This gives an average ~1.3% code size improvement on CINT2000 at -O3. Differential Revision: https://reviews.llvm.org/D64108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365063 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index f03e0f39a0b..eaae7201a40 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -3777,13 +3777,11 @@ static Optional getImmedFromMO(const MachineOperand &Root) { else if (Root.isCImm()) Immed = Root.getCImm()->getZExtValue(); else if (Root.isReg()) { - MachineInstr *Def = MRI.getVRegDef(Root.getReg()); - if (Def->getOpcode() != TargetOpcode::G_CONSTANT) - return None; - MachineOperand &Op1 = Def->getOperand(1); - if (!Op1.isCImm() || Op1.getCImm()->getBitWidth() > 64) + auto ValAndVReg = + getConstantVRegValWithLookThrough(Root.getReg(), MRI, true); + if (!ValAndVReg) return None; - Immed = Op1.getCImm()->getZExtValue(); + Immed = ValAndVReg->Value; } else return None; return Immed; diff --git a/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/test/CodeGen/AArch64/GlobalISel/select-cmp.mir index 456216d6a2d..ef1e658c467 100644 --- a/test/CodeGen/AArch64/GlobalISel/select-cmp.mir +++ b/test/CodeGen/AArch64/GlobalISel/select-cmp.mir @@ -70,3 +70,47 @@ body: | RET_ReallyLR implicit $w0 ... +--- +name: cmp_imm_lookthrough +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $w0 + ; CHECK-LABEL: name: cmp_imm_lookthrough + ; CHECK: liveins: $w0 + ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 + ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv + ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv + ; CHECK: $w0 = COPY [[CSINCWr]] + ; CHECK: RET_ReallyLR implicit $w0 + %0:gpr(s32) = COPY $w0 + %1:gpr(s64) = G_CONSTANT i64 42 + %2:gpr(s32) = G_TRUNC %1(s64) + %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2 + $w0 = COPY %5(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: cmp_imm_lookthrough_bad_trunc +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $w0 + ; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc + ; CHECK: liveins: $w0 + ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 + ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv + ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv + ; CHECK: $w0 = COPY [[CSINCWr]] + ; CHECK: RET_ReallyLR implicit $w0 + %0:gpr(s32) = COPY $w0 + %1:gpr(s64) = G_CONSTANT i64 68719476736 ; 0x1000000000 + %2:gpr(s32) = G_TRUNC %1(s64) ; Value truncates to 0 + %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2 + $w0 = COPY %5(s32) + RET_ReallyLR implicit $w0 diff --git a/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir index 813253748f8..85b32e12903 100644 --- a/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +++ b/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir @@ -57,19 +57,16 @@ body: | ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0 - ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 71 - ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 0 + ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32 - ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31 - ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 - ; CHECK: [[UBFMXri1:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG1]], 0, 31 - ; CHECK: $xzr = SUBSXrr [[UBFMXri]], [[UBFMXri1]], implicit-def $nzcv + ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[SUBREG_TO_REG]], 0, 31 + ; CHECK: $xzr = SUBSXri [[UBFMXri]], 71, 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK: TBNZW [[CSINCWr]], 0, %bb.4 ; CHECK: bb.1.entry: ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab) - ; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 0 + ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 0 ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0 ; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[UBFMXri]], %jump-table.0 ; CHECK: BR %18 @@ -79,10 +76,10 @@ body: | ; CHECK: B %bb.4 ; CHECK: bb.3.sw.bb1: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: [[MOVi32imm3:%[0-9]+]]:gpr32 = MOVi32imm 3 - ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[MOVi32imm3]], $wzr + ; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 3 + ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[MOVi32imm2]], $wzr ; CHECK: bb.4.return: - ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[MOVi32imm1]], %bb.0, [[MOVi32imm2]], %bb.1 + ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[MOVi32imm]], %bb.0, [[MOVi32imm1]], %bb.1 ; CHECK: $w0 = COPY [[PHI]] ; CHECK: RET_ReallyLR implicit $w0 bb.1.entry: