From: Diana Picus <diana.picus@linaro.org>
Date: Fri, 24 Feb 2017 13:07:25 +0000 (+0000)
Subject: [ARM] GlobalISel: Add reg bank mappings for stores
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=11601c0bd39bde38190f4523c73d3e8107900aaf;p=llvm

[ARM] GlobalISel: Add reg bank mappings for stores

Same as the ones for loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296115 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMRegisterBankInfo.cpp b/lib/Target/ARM/ARMRegisterBankInfo.cpp
index d66bc4644c2..8a53e719c36 100644
--- a/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -181,6 +181,7 @@ const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
   case GPRRegClassID:
   case GPRnopcRegClassID:
   case tGPR_and_tcGPRRegClassID:
+  case tGPRRegClassID:
     return getRegBank(ARM::GPRRegBankID);
   case SPR_8RegClassID:
   case SPRRegClassID:
@@ -224,6 +225,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
     break;
   case G_LOAD:
+  case G_STORE:
     OperandsMapping =
         Ty.getSizeInBits() == 64
             ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index e54ca39b3ae..b9634f8e7f1 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -6,6 +6,7 @@
   define void @test_add_s1() { ret void }
 
   define void @test_loads() #0 { ret void }
+  define void @test_stores() #0 { ret void }
 
   define void @test_fadd_s32() #0 { ret void }
   define void @test_fadd_s64() #0 { ret void }
@@ -153,6 +154,48 @@ body:             |
     %5(p0)  = G_LOAD %0 :: (load 8)
     BX_RET 14, _, implicit %r0
 
+...
+---
+name:            test_stores
+# CHECK-LABEL: name: test_stores
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 6, class: fprb }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+  - { id: 6, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2, %r3, %r4, %r5, %d6
+    %0(p0) = COPY %r0
+    %1(s32) = COPY %r1
+    G_STORE %1(s32), %0 :: (store 4)
+    %2(s16) = COPY %r2
+    G_STORE %2(s16), %0 :: (store 2)
+    %3(s8) = COPY %r3
+    G_STORE %3(s8), %0 :: (store 1)
+    %4(s1) = COPY %r4
+    G_STORE %4(s1), %0 :: (store 1)
+    %5(p0) = COPY %r5
+    G_STORE %5(p0), %0 :: (store 8)
+    %6(s64) = COPY %d6
+    G_STORE %6(s64), %0 :: (store 8)
+    BX_RET 14, _, implicit %r0
+
 ...
 ---
 name:            test_fadd_s32