From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 10 Dec 2017 11:51:29 +0000 (+0000)
Subject: [X86] Flag BTVER2 scheduler model as complete
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0f9bf7085ca263ac3f6d5a1cf41577f27396a003;p=llvm

[X86] Flag BTVER2 scheduler model as complete

We just have to locally tag COPY as WriteMove

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320300 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ScheduleBtVer2.td b/lib/Target/X86/X86ScheduleBtVer2.td
index 685aaf1f140..d7474a28896 100644
--- a/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/lib/Target/X86/X86ScheduleBtVer2.td
@@ -22,10 +22,6 @@ def BtVer2Model : SchedMachineModel {
   let HighLatency = 25;
   let MispredictPenalty = 14; // Minimum branch misdirection penalty
   let PostRAScheduler = 1;
-
-  // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
-  // the scheduler to assign a default model to unrecognized opcodes.
-  let CompleteModel = 0;
 }
 
 let SchedModel = BtVer2Model in {
@@ -168,6 +164,9 @@ def : WriteRes<WriteLoad,  [JLAGU]> { let Latency = 5; }
 def : WriteRes<WriteStore, [JSAGU]>;
 def : WriteRes<WriteMove,  [JALU01]>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 ////////////////////////////////////////////////////////////////////////////////
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.