From: Ivan Grokhotkov Date: Wed, 12 Dec 2018 04:22:48 +0000 (+0800) Subject: soc/rtc: reset another BBPLL related register X-Git-Tag: v3.3-beta2~146^2 X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0cf8d1380ec6bad7b231dd130bd44c9f8faef0a5;p=esp-idf soc/rtc: reset another BBPLL related register Follow-up to b21ffc8a: an additional register needs to be reset. Ref. https://github.com/espressif/esp-idf/issues/2711 --- diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 2c462ed402..0afde2cff6 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -48,7 +48,7 @@ #define BBPLL_IR_CAL_EXT_CAP_VAL 0x20 #define BBPLL_OC_ENB_FCAL_VAL 0x9a #define BBPLL_OC_ENB_VCON_VAL 0x00 - +#define BBPLL_BBADC_CAL_7_0_VAL 0x00 #define APLL_SDM_STOP_VAL_1 0x09 #define APLL_SDM_STOP_VAL_2_REV0 0x69 @@ -441,6 +441,7 @@ static void rtc_clk_bbpll_enable() I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL); I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL); I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL); } /**