From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 21 May 2019 23:23:12 +0000 (+0000)
Subject: AMDGPU: Add some tests for inlineasm behavior
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0cd028a8d520da4691e76145170dd0f69d8e481f;p=llvm

AMDGPU: Add some tests for inlineasm behavior

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361332 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AMDGPU/endpgm-dce.mir b/test/CodeGen/AMDGPU/endpgm-dce.mir
index c8c05e471f1..7733b0487cf 100644
--- a/test/CodeGen/AMDGPU/endpgm-dce.mir
+++ b/test/CodeGen/AMDGPU/endpgm-dce.mir
@@ -313,3 +313,46 @@ body:             |
     S_ENDPGM 0, implicit %3
 
 ...
+
+---
+# GCN-LABEL: name: inlineasm_nosideeffect
+# GCN-NOT: S_OR_B64
+# GCN-NOT: INLINEASM
+# GCN: S_ENDPGM 0
+name: inlineasm_nosideeffect
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vreg_64 }
+  - { id: 1, class: vgpr_32 }
+body:             |
+  bb.0:
+    $vcc = IMPLICIT_DEF
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
+    %2:sreg_64 = IMPLICIT_DEF
+    INLINEASM &"", 0, 0
+    S_ENDPGM 0
+...
+
+---
+# GCN-LABEL: name: inlineasm_sideeffect
+# GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
+# GCN-NEXT: IMPLICIT_DEF
+# GCN-NEXT: INLINEASM
+# GCN-NEXT: S_ENDPGM 0
+name: inlineasm_sideeffect
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vreg_64 }
+  - { id: 1, class: vgpr_32 }
+body:             |
+  bb.0:
+    $vcc = IMPLICIT_DEF
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
+    %2:sreg_64 = IMPLICIT_DEF
+    INLINEASM &"", 1, 0
+    S_ENDPGM 0
+...