From: Oliver Stannard Date: Mon, 9 Sep 2019 08:50:28 +0000 (+0000) Subject: [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0be4de0ae5c4a6ea9036923a7a0a9a37289698a9;p=llvm [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings Specify the Unpredictable bits, and return softfails when appropriate. Patch by Mark Murray! Differential revision: https://reviews.llvm.org/D66939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371374 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrMVE.td b/lib/Target/ARM/ARMInstrMVE.td index 9cb6b4fc164..f25aadc468c 100644 --- a/lib/Target/ARM/ARMInstrMVE.td +++ b/lib/Target/ARM/ARMInstrMVE.td @@ -373,6 +373,8 @@ class MVE_ScalarShiftSRegReg op5_4, list pattern=[]> let Inst{7-6} = 0b00; let Inst{5-4} = op5_4{1-0}; let Inst{3-0} = 0b1101; + + let Unpredictable{8-6} = 0b111; } def MVE_SQRSHR : MVE_ScalarShiftSRegReg<"sqrshr", 0b10>; diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index e027fd6906e..eabc26d05f4 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -6483,6 +6483,12 @@ static DecodeStatus DecodeMVEOverlappingLongShift( if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; + if (fieldFromInstruction (Insn, 6, 3) != 4) + return MCDisassembler::SoftFail; + + if (Rda == Rm) + return MCDisassembler::SoftFail; + return S; } diff --git a/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt b/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt new file mode 100644 index 00000000000..408bcf99832 --- /dev/null +++ b/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt @@ -0,0 +1,42 @@ +# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK %s +# RUN: FileCheck --check-prefix=STDERR < %t %s + +[0x5e 0xea 0x6d 0xcf] +# CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x5e 0xea 0xad 0xcf] +# CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x5e 0xea 0xed 0xcf] +# CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x5e 0xea 0x2d 0xce] +# CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x51 0xea 0x2d 0x1f] +# CHECK: sqrshr r1, r1 @ encoding: [0x51,0xea,0x2d,0x1f] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x5e 0xea 0x4d 0xcf] +# CHECK: uqrshl lr, r12 @ encoding: [0x5e,0xea,0x0d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x5b 0xea 0x8d 0xcf] +# CHECK: uqrshl r11, r12 @ encoding: [0x5b,0xea,0x0d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x5e 0xea 0xcd 0xcf] +# CHECK: uqrshl lr, r12 @ encoding: [0x5e,0xea,0x0d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x5b 0xea 0x0d 0xce] +# CHECK: uqrshl r11, r12 @ encoding: [0x5b,0xea,0x0d,0xcf] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x53 0xea 0x0d 0x3f] +# CHECK: uqrshl r3, r3 @ encoding: [0x53,0xea,0x0d,0x3f] +# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding