From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 24 Jun 2019 18:00:47 +0000 (+0000)
Subject: AMDGPU/GlobalISel: RegBankSelect for amdgcn.class
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0bb983e6aeca4434ce2a4e928c96b6fb1e9905ae;p=llvm

AMDGPU/GlobalISel: RegBankSelect for amdgcn.class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364214 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 7cfd580e81e..b5ff27ed0b4 100644
--- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1502,6 +1502,15 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
       break;
     }
+    case Intrinsic::amdgcn_class: {
+      unsigned SrcReg = MI.getOperand(2).getReg();
+      unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
+      unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+      OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize);
+      OpdsMapping[2] = AMDGPU::getValueMapping(getRegBankID(SrcReg, MRI, *TRI),
+                                               SrcSize);
+      break;
+    }
     }
     break;
   }
diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
new file mode 100644
index 00000000000..d28f06175ad
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: class_s
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: class_s
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
+...
+
+---
+name: class_v
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: class_v
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
+...