From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 23 Jun 2016 07:37:26 +0000 (+0000)
Subject: [X86] Add assert to ensure only 128-bit vector types are used. 256 or 512-bit would... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0b27eaff680156c7a3c9b21f124d167296004806;p=llvm

[X86] Add assert to ensure only 128-bit vector types are used. 256 or 512-bit would require lane handling which is missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273542 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 11b98003f57..54e5536c36e 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4684,6 +4684,7 @@ static SDValue getOnesVector(EVT VT, const X86Subtarget &Subtarget,
 /// Returns a vector_shuffle node for an unpackl operation.
 static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
                           SDValue V1, SDValue V2) {
+  assert(VT.is128BitVector() && "Expected a 128-bit vector type");
   unsigned NumElems = VT.getVectorNumElements();
   SmallVector<int, 8> Mask(NumElems);
   for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
@@ -4696,6 +4697,7 @@ static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
 /// Returns a vector_shuffle node for an unpackh operation.
 static SDValue getUnpackh(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
                           SDValue V1, SDValue V2) {
+  assert(VT.is128BitVector() && "Expected a 128-bit vector type");
   unsigned NumElems = VT.getVectorNumElements();
   SmallVector<int, 8> Mask(NumElems);
   for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {