From: Kadir Cetinkaya <kadircet@google.com>
Date: Thu, 28 Feb 2019 15:55:11 +0000 (+0000)
Subject: [Target][ARM] Add a usage for SrcSz to unbreak build-bots without assertions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0ad049beeaf1d313e9b449a3216e39258fdaf636;p=llvm

[Target][ARM] Add a usage for SrcSz to unbreak build-bots without assertions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355101 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 524b84ec6f2..d8764f6f7ab 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -13701,6 +13701,7 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     EVT VT = Op.getValueType();
     const unsigned DstSz = VT.getScalarSizeInBits();
     const unsigned SrcSz = VecVT.getVectorElementType().getSizeInBits();
+    (void)SrcSz;
     assert(SrcSz == Known.getBitWidth());
     assert(DstSz > SrcSz);
     if (Op.getOpcode() == ARMISD::VGETLANEs)