From: Quentin Colombet <qcolombet@apple.com>
Date: Tue, 11 Oct 2016 00:21:11 +0000 (+0000)
Subject: [AArch64][InstructionSelector] Teach the selector how to handle vector OR.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=082e838555b1ebe4055cd1bf8bb3e95012c753b6;p=llvm

[AArch64][InstructionSelector] Teach the selector how to handle vector OR.

This only adds the support for 64-bit vector OR. Adding more sizes is
not difficult, but it requires a bigger refactoring because ORs work on
any size, not necessarly the ones that match the width of the register
width. Right now, this is not expressed in the legalization, so don't
bother pushing the refactoring yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283831 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index b534f248e40..c8a00199e27 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -175,6 +175,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
         return AArch64::FMULDrr;
       case TargetOpcode::G_FDIV:
         return AArch64::FDIVDrr;
+      case TargetOpcode::G_OR:
+        return AArch64::ORRv8i8;
       default:
         return GenericOpc;
       }
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
index 8f280ecf88a..d4b81b920af 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -15,6 +15,7 @@
 
   define void @or_s32_gpr() { ret void }
   define void @or_s64_gpr() { ret void }
+  define void @or_v2s32_fpr() { ret void }
 
   define void @xor_s32_gpr() { ret void }
   define void @xor_s64_gpr() { ret void }
@@ -254,6 +255,37 @@ body:             |
     %2(s64) = G_OR %0, %1
 ...
 
+---
+# 64-bit G_OR on vector registers.
+# CHECK-LABEL: name: or_v2s32_fpr
+name:            or_v2s32_fpr
+legalized:       true
+regBankSelected: true
+#
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr64 }
+# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 2, class: fpr64 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %d0
+# CHECK:    %1 = COPY %d1
+# The actual OR does not matter as long as it is operating
+# on 64-bit width vector.
+# CHECK:    %2 = ORRv8i8 %0, %1
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+      %0(<2 x s32>) = COPY %d0
+      %1(<2 x s32>) = COPY %d1
+      %2(<2 x s32>) = G_OR %0, %1
+...
+
 ---
 # Same as add_s32_gpr, for G_XOR operations.
 # CHECK-LABEL: name: xor_s32_gpr