From: Tim Northover <tnorthover@apple.com>
Date: Tue, 14 Feb 2017 20:56:29 +0000 (+0000)
Subject: GlobalISel: deal with new G_PTR_MASK instruction on AArch64.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=07fb294d72bcb95081bcee5023a79c028b3210a2;p=llvm

GlobalISel: deal with new G_PTR_MASK instruction on AArch64.

It's just an AND-immediate instruction for us, surprisingly simple to select.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295104 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 6bced17d09d..f83c7f0e6cc 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -816,6 +816,17 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
+  case TargetOpcode::G_PTR_MASK: {
+    uint64_t Align = I.getOperand(2).getImm();
+    if (Align >= 64 || Align == 0)
+      return false;
+
+    uint64_t Mask = ~((1ULL << Align) - 1);
+    I.setDesc(TII.get(AArch64::ANDXri));
+    I.getOperand(2).setImm(AArch64_AM::encodeLogicalImmediate(Mask, 64));
+
+    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+  }
   case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_TRUNC: {
     const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
diff --git a/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index c978be9ab10..fc224d22a13 100644
--- a/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -52,6 +52,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() {
   for (auto Ty : {s1, s8, s16, s32})
     setAction({G_GEP, 1, Ty}, WidenScalar);
 
+  setAction({G_PTR_MASK, p0}, Legal);
+
   for (unsigned BinOp : {G_LSHR, G_ASHR, G_SDIV, G_UDIV}) {
     for (auto Ty : {s32, s64})
       setAction({BinOp, Ty}, Legal);
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
index c07dd60ee6a..55329aa5b27 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -114,6 +114,8 @@
 
   define i8* @gep(i8* %in) { ret i8* undef }
 
+  define i8* @ptr_mask(i8* %in) { ret i8* undef }
+
   @var_local = global i8 0
   define i8* @global_local() { ret i8* undef }
 
@@ -2043,6 +2045,21 @@ body:             |
     %2(p0) = G_GEP %0, %1(s64)
 ...
 
+---
+# CHECK-LABEL: name: ptr_mask
+name:            ptr_mask
+legalized:       true
+regBankSelected: true
+
+# CHECK:  body:
+# CHECK: %1 = ANDXri %0, 8060
+body:             |
+  bb.0:
+      liveins: %x0
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(p0) = G_PTR_MASK %0, 3
+...
+
 ---
 # Global defined in the same linkage unit so no GOT is needed
 # CHECK-LABEL: name: global_local