From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 19 Jun 2019 11:17:48 +0000 (+0000)
Subject: [DAGCombine] Fix (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) comment... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=07e51b46a78954e93442ed360c97ae7e4f58287d;p=llvm

[DAGCombine] Fix (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) comment. NFCI.

We pre-extend, not post.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363787 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 63f3df8f0cc..ebb79ef9e48 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7167,6 +7167,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   if (DAG.MaskedValueIsZero(SDValue(N, 0),
                             APInt::getAllOnesValue(OpSizeInBits)))
     return DAG.getConstant(0, SDLoc(N), VT);
+
   // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
   if (N1.getOpcode() == ISD::TRUNCATE &&
       N1.getOperand(0).getOpcode() == ISD::AND) {
@@ -7204,7 +7205,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
     }
   }
 
-  // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
+  // fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2))
   // For this to be valid, the second form must not preserve any of the bits
   // that are shifted out by the inner shift in the first form.  This means
   // the outer shift size must be >= the number of bits added by the ext.
diff --git a/test/CodeGen/X86/combine-shl.ll b/test/CodeGen/X86/combine-shl.ll
index 3e54d29cef9..8e84cfa25f2 100644
--- a/test/CodeGen/X86/combine-shl.ll
+++ b/test/CodeGen/X86/combine-shl.ll
@@ -233,7 +233,7 @@ define <4 x i32> @combine_vec_shl_shl_zero1(<4 x i32> %x) {
   ret <4 x i32> %2
 }
 
-; fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
+; fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2))
 define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) {
 ; SSE2-LABEL: combine_vec_shl_ext_shl0:
 ; SSE2:       # %bb.0: