From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 21 Jun 2019 16:11:18 +0000 (+0000)
Subject: Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0705bbc6fe3f1a9e25c93ac4a2236bf8102adc12;p=llvm

Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364068 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index fd99704af2b..acabfd32cd7 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -6148,7 +6148,7 @@ static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
   if (Val < MinLog || Val > MaxLog)
     return MCDisassembler::Fail;
 
-  Inst.addOperand(MCOperand::createImm(1 << Val));
+  Inst.addOperand(MCOperand::createImm(1LL << Val));
   return S;
 }