From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 6 Dec 2016 15:57:26 +0000 (+0000)
Subject: [X86][SSE] Added vector sext_in_reg combine tests
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=06ec4e5b99cb68505ee02fd9c0131de80b573fd2;p=llvm

[X86][SSE] Added vector sext_in_reg combine tests


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288819 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/combine-sext-in-reg.ll b/test/CodeGen/X86/combine-sext-in-reg.ll
new file mode 100644
index 00000000000..9407d1bb4e7
--- /dev/null
+++ b/test/CodeGen/X86/combine-sext-in-reg.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
+
+; fold sextinreg(zext) -> sext
+define <4 x i64> @sextinreg_zext_v16i8_4i64(<16 x i8> %a0) {
+; SSE-LABEL: sextinreg_zext_v16i8_4i64:
+; SSE:       # BB#0:
+; SSE-NEXT:    pmovsxbq %xmm0, %xmm2
+; SSE-NEXT:    psrld $16, %xmm0
+; SSE-NEXT:    pmovsxbq %xmm0, %xmm1
+; SSE-NEXT:    movdqa %xmm2, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: sextinreg_zext_v16i8_4i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovsxbq %xmm0, %ymm0
+; AVX-NEXT:    retq
+  %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %2 = zext <4 x i8> %1 to <4 x i64>
+  %3 = shl <4 x i64> %2, <i64 56, i64 56, i64 56, i64 56>
+  %4 = ashr <4 x i64> %3, <i64 56, i64 56, i64 56, i64 56>
+  ret <4 x i64> %4
+}
+
+; fold sextinreg(zext(sext)) -> sext
+define <4 x i64> @sextinreg_zext_sext_v16i8_4i64(<16 x i8> %a0) {
+; SSE-LABEL: sextinreg_zext_sext_v16i8_4i64:
+; SSE:       # BB#0:
+; SSE-NEXT:    pmovsxbq %xmm0, %xmm2
+; SSE-NEXT:    psrld $16, %xmm0
+; SSE-NEXT:    pmovsxbq %xmm0, %xmm1
+; SSE-NEXT:    psllq $32, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; SSE-NEXT:    psrad $31, %xmm2
+; SSE-NEXT:    pblendw {{.*#+}} xmm2 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; SSE-NEXT:    psllq $32, %xmm1
+; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; SSE-NEXT:    psrad $31, %xmm1
+; SSE-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; SSE-NEXT:    movdqa %xmm2, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: sextinreg_zext_sext_v16i8_4i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovsxbq %xmm0, %ymm0
+; AVX-NEXT:    vpsllq $32, %ymm0, %ymm0
+; AVX-NEXT:    vpsrad $31, %ymm0, %ymm1
+; AVX-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
+; AVX-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
+; AVX-NEXT:    retq
+  %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %2 = sext <4 x i8> %1 to <4 x i32>
+  %3 = zext <4 x i32> %2 to <4 x i64>
+  %4 = shl <4 x i64> %3, <i64 32, i64 32, i64 32, i64 32>
+  %5 = ashr <4 x i64> %4, <i64 32, i64 32, i64 32, i64 32>
+  ret <4 x i64> %5
+}