From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Wed, 22 Jun 2016 16:07:10 +0000 (+0000)
Subject: [Hexagon] Handle expansion of cmpxchg
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=065537a5a0aa92ef46b40b23b559a975f1b089f4;p=llvm

[Hexagon] Handle expansion of cmpxchg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273432 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index b29a43d8aae..42feffc3201 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1715,6 +1715,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setMinFunctionAlignment(2);
   setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
 
+  setMaxAtomicSizeInBitsSupported(64);
+  setMinCmpXchgSizeInBits(32);
+
   if (EnableHexSDNodeSched)
     setSchedulingPreference(Sched::VLIW);
   else
@@ -3121,3 +3124,10 @@ bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
   // Do not expand loads and stores that don't exceed 64 bits.
   return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
 }
+
+bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
+      AtomicCmpXchgInst *AI) const {
+  const DataLayout &DL = AI->getModule()->getDataLayout();
+  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
+  return Size >= 4 && Size <= 8;
+}
diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h
index e94c077c842..83a374ca0fb 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/lib/Target/Hexagon/HexagonISelLowering.h
@@ -256,6 +256,8 @@ bool isPositiveHalfWord(SDNode *N);
         Value *Addr, AtomicOrdering Ord) const override;
     AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
+    bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
+
     AtomicExpansionKind
     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
       return AtomicExpansionKind::LLSC;
diff --git a/test/CodeGen/Hexagon/Atomics.ll b/test/CodeGen/Hexagon/Atomics.ll
index bbac5d73c86..cedf9a48754 100644
--- a/test/CodeGen/Hexagon/Atomics.ll
+++ b/test/CodeGen/Hexagon/Atomics.ll
@@ -69,3 +69,16 @@ entry:
 return:                                           ; preds = %entry
   ret void
 }
+
+
+define i64 @fred() nounwind {
+entry:
+  %s0 = cmpxchg i32* undef, i32 undef, i32 undef seq_cst seq_cst
+  %s1 = extractvalue { i32, i1 } %s0, 0
+  %t0 = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst
+  %t1 = extractvalue { i64, i1 } %t0, 0
+  %u0 = zext i32 %s1 to i64
+  %u1 = add i64 %u0, %t1
+  ret i64 %u1
+}
+