From: Diana Picus <diana.picus@linaro.org>
Date: Thu, 21 Feb 2019 13:00:02 +0000 (+0000)
Subject: [ARM GlobalISel] Support G_FRAME_INDEX for Thumb2
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=063c3128bcc41362fce4d158c82667e8a1a7cbd8;p=llvm

[ARM GlobalISel] Support G_FRAME_INDEX for Thumb2

Same as arm mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354579 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp
index 0c95c21054d..091f1ff807d 100644
--- a/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -98,6 +98,7 @@ private:
     unsigned LOAD8;
 
     unsigned ADDrr;
+    unsigned ADDri;
 
     // Used for G_ICMP
     unsigned CMPrr;
@@ -300,6 +301,7 @@ ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {
   STORE_OPCODE(LOAD8, LDRBi12);
 
   STORE_OPCODE(ADDrr, ADDrr);
+  STORE_OPCODE(ADDri, ADDri);
 
   STORE_OPCODE(CMPrr, CMPrr);
   STORE_OPCODE(MOVi, MOVi);
@@ -967,7 +969,7 @@ bool ARMInstructionSelector::select(MachineInstr &I,
   case G_FRAME_INDEX:
     // Add 0 to the given frame index and hope it will eventually be folded into
     // the user(s).
-    I.setDesc(TII.get(ARM::ADDri));
+    I.setDesc(TII.get(Opcodes.ADDri));
     MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
     break;
   case G_GLOBAL_VALUE:
diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp
index 5427c7fc0bb..1154d358bd3 100644
--- a/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -138,6 +138,8 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
               {s32, p0, 32, 8},
               {p0, p0, 32, 8}});
 
+  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
+
   auto &PhiBuilder =
       getActionDefinitionsBuilder(G_PHI)
           .legalFor({s32, p0})
@@ -155,7 +157,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
   }
 
   getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
-  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
 
   if (ST.hasV5TOps()) {
     getActionDefinitionsBuilder(G_CTLZ)
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
index a3b4fece523..34ed8b84307 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
@@ -2,6 +2,7 @@
 # RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
 --- |
   define void @test_legal_loads_stores() { ret void }
+  define void @test_load_from_stack() { ret void }
 
   define void @test_gep() { ret void }
 ...
@@ -50,6 +51,36 @@ body:             |
     BX_RET 14, $noreg
 ...
 ---
+name:            test_load_from_stack
+# CHECK-LABEL: name: test_load_from_stack
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+fixedStack:
+  - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  # CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
+body:             |
+  bb.0:
+    liveins: $r0, $r1, $r2, $r3
+
+    ; This is legal, so we should find it unchanged in the output
+    ; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
+    %0(p0) = G_FRAME_INDEX %fixed-stack.2
+    %1(s32) = G_LOAD %0(p0) :: (load 4)
+    $r0 = COPY %1(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
 name:            test_gep
 # CHECK-LABEL: name: test_gep
 legalized:       false
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index 36fc40e797f..1d77b7936bf 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -1,6 +1,5 @@
 # RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
 --- |
-  define void @test_load_from_stack() { ret void }
   define void @test_load_store_64() #0 { ret void }
 
   define void @test_constants_s64() { ret void }
@@ -13,36 +12,6 @@
   attributes #0 = { "target-features"="+vfp2" }
 ...
 ---
-name:            test_load_from_stack
-# CHECK-LABEL: name: test_load_from_stack
-legalized:       false
-# CHECK: legalized: true
-regBankSelected: false
-selected:        false
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-fixedStack:
-  - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-  - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-  - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-  # CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
-body:             |
-  bb.0:
-    liveins: $r0, $r1, $r2, $r3
-
-    ; This is legal, so we should find it unchanged in the output
-    ; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
-    ; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
-    %0(p0) = G_FRAME_INDEX %fixed-stack.2
-    %1(s32) = G_LOAD %0(p0) :: (load 4)
-    $r0 = COPY %1(s32)
-    BX_RET 14, $noreg, implicit $r0
-...
----
 name:            test_load_store_64
 # CHECK-LABEL: name: test_load_store_64
 legalized:       false
diff --git a/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir b/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
index ec64c8a2c1e..0a6ddb352a6 100644
--- a/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
+++ b/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
@@ -5,6 +5,8 @@
   define void @test_s32() { ret void }
 
   define void @test_gep() { ret void }
+
+  define void @test_load_from_stack() { ret void }
 ...
 ---
 name:            test_s8
@@ -114,3 +116,50 @@ body:             |
     BX_RET 14, $noreg, implicit $r0
     ; CHECK: BX_RET 14, $noreg, implicit $r0
 ...
+---
+name:            test_load_from_stack
+# CHECK-LABEL: name: test_load_from_stack
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+fixedStack:
+  - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
+# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
+body:             |
+  bb.0:
+    liveins: $r0, $r1, $r2, $r3
+
+    %0(p0) = G_FRAME_INDEX %fixed-stack.2
+    ; CHECK: [[FI32VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
+
+    %1(s32) = G_LOAD %0(p0) :: (load 4)
+    ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = t2LDRi12 [[FI32VREG]], 0, 14, $noreg
+
+    $r0 = COPY %1
+    ; CHECK: $r0 = COPY [[LD32VREG]]
+
+    %2(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; CHECK: [[FI1VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
+
+    %3(s1) = G_LOAD %2(p0) :: (load 1)
+    ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = t2LDRBi12 [[FI1VREG]], 0, 14, $noreg
+
+    %4(s32) = G_ANYEXT %3(s1)
+    ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
+
+    $r0 = COPY %4
+    ; CHECK: $r0 = COPY [[RES]]
+
+    BX_RET 14, $noreg
+    ; CHECK: BX_RET 14, $noreg
+...