From: Craig Topper <craig.topper@intel.com>
Date: Mon, 28 Aug 2017 05:14:38 +0000 (+0000)
Subject: [X86] Use getUnpackl helper to create an ISD::VECTOR_SHUFFLE instead of using X86ISD... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=038b48711268a0ee26d2ab68ada4745aaa1d5275;p=llvm

[X86] Use getUnpackl helper to create an ISD::VECTOR_SHUFFLE instead of using X86ISD::UNPCKL in reduceVMULWidth.

This runs fairly early, we should use target independent nodes if possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311873 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c9afea2d163..9616220171a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -31373,7 +31373,7 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
       // Repack the lower part and higher part result of mul into a wider
       // result. Make sure the type of mul result is VT.
       MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32);
-      SDValue Res = DAG.getNode(X86ISD::UNPCKL, DL, OpsVT, MulLo, MulHi);
+      SDValue Res = getUnpackl(DAG, DL, OpsVT, MulLo, MulHi);
       Res = DAG.getNode(ISD::BITCAST, DL, ResVT, Res);
       return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
                          DAG.getIntPtrConstant(0, DL));