From: Mikhail Maltsev <mikhail.maltsev@arm.com>
Date: Wed, 10 Jul 2019 08:59:17 +0000 (+0000)
Subject: [ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=035937569b759d976d64e4278af43187e6a1d044;p=llvm

[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present

Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.

Patch by Momchil Velikov.

Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen

Reviewed By: dmgreen

Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365604 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index f889382073e..bc93a058720 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -2591,7 +2591,7 @@ class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
 // VFP/NEON Instruction aliases for type suffices.
 // Note: When EmitPriority == 1, the alias will be used for printing
 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> :
-  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>;
+  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasFPRegs]>;
 
 // Note: When EmitPriority == 1, the alias will be used for printing
 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index ea31e631d3a..93c27e46300 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -302,13 +302,13 @@ def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
 }
 
 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
                          (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
diff --git a/test/MC/ARM/mve-fp-registers.s b/test/MC/ARM/mve-fp-registers.s
index ea2c88c503f..745c464183f 100644
--- a/test/MC/ARM/mve-fp-registers.s
+++ b/test/MC/ARM/mve-fp-registers.s
@@ -45,18 +45,50 @@ vldmia  r0, {d0}
 # FP32: vldmia  r0, {d0}               @ encoding: [0x90,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.64    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {d0}
 # FP32: vstmia  r0, {d0}                @ encoding: [0x80,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.64    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vldmia  r0, {s0}
 # FP32: vldmia  r0, {s0}                @ encoding: [0x90,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.32 {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {s0}
 # FP32: vstmia  r0, {s0}                @ encoding: [0x80,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.32 {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 fldmdbx r0!, {d0}
 # FP32: fldmdbx r0!, {d0}               @ encoding: [0x30,0xed,0x03,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers