From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 22 Jan 2019 16:26:09 +0000 (+0000)
Subject: [x86] add another partial undef vector binop test; NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=02f4bb54c2de68e29bf06097dae049caaf33d1ec;p=llvm

[x86] add another partial undef vector binop test; NFC

The existing test unintentionally shows that we have prematurely
optimized the shuffle into a vector concat and lost the undef info,
so it is not affected by a basic improvement to
SimplifyDemandedVectorElts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351834 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/vector-partial-undef.ll b/test/CodeGen/X86/vector-partial-undef.ll
index 2b4ab11fea5..3c4acf72219 100644
--- a/test/CodeGen/X86/vector-partial-undef.ll
+++ b/test/CodeGen/X86/vector-partial-undef.ll
@@ -109,6 +109,37 @@ define <4 x i64> @or_undef_elts(<2 x i64> %x) {
 define <8 x i32> @xor_undef_elts(<4 x i32> %x) {
 ; SSE-LABEL: xor_undef_elts:
 ; SSE:       # %bb.0:
+; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[0,2,2,3]
+; SSE-NEXT:    pxor {{.*}}(%rip), %xmm2
+; SSE-NEXT:    pxor {{.*}}(%rip), %xmm1
+; SSE-NEXT:    movdqa %xmm1, %xmm0
+; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[2,0]
+; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[1,0]
+; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[3,0],xmm1[0,0]
+; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm2[2,0]
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: xor_undef_elts:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,3,0,2]
+; AVX-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3]
+; AVX-NEXT:    vxorps {{.*}}(%rip), %ymm0, %ymm0
+; AVX-NEXT:    vmovaps {{.*#+}} ymm1 = [6,1,5,4,3,2,0,7]
+; AVX-NEXT:    vpermps %ymm0, %ymm1, %ymm0
+; AVX-NEXT:    retq
+  %extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 1, i32 3, i32 0, i32 2, i32 undef, i32 undef>
+  %bogus_bo = xor <8 x i32> %extend, <i32 42, i32 43, i32 undef, i32 undef, i32 undef, i32 undef, i32 44, i32 12>
+  %arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 6, i32 1, i32 5, i32 4, i32 3, i32 2, i32 0, i32 7>
+  ret <8 x i32> %arbitrary_shuf
+}
+
+; Verify that this isn't limited to high/low halves
+; Special case: the undef-ness of the 1st shuffle may be lost if we turn that into vector concat.
+
+define <8 x i32> @xor_undef_elts_alt(<4 x i32> %x) {
+; SSE-LABEL: xor_undef_elts_alt:
+; SSE:       # %bb.0:
 ; SSE-NEXT:    movaps %xmm0, %xmm1
 ; SSE-NEXT:    movaps {{.*#+}} xmm2 = <u,u,44,12>
 ; SSE-NEXT:    xorps %xmm0, %xmm2
@@ -120,7 +151,7 @@ define <8 x i32> @xor_undef_elts(<4 x i32> %x) {
 ; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm2[2,0]
 ; SSE-NEXT:    retq
 ;
-; AVX-LABEL: xor_undef_elts:
+; AVX-LABEL: xor_undef_elts_alt:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
 ; AVX-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0