From: Simon Atanasyan <simon@atanasyan.com>
Date: Wed, 3 Jul 2019 12:27:58 +0000 (+0000)
Subject: [mips] Add missing atomic instructions to general scheduling definitions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=028b9a86d99e6fa73452ebc0efe63807471b745c;p=llvm

[mips] Add missing atomic instructions to general scheduling definitions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365033 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsScheduleGeneric.td b/lib/Target/Mips/MipsScheduleGeneric.td
index 137087e3bf9..58a7b0b38d2 100644
--- a/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/lib/Target/Mips/MipsScheduleGeneric.td
@@ -1595,4 +1595,20 @@ def : InstRW<[GenericWriteFPUStore], (instregex "^ST_[BHWD]$")>;
 def : InstRW<[GenericWriteFPUStore], (instrs ST_F16)>;
 def : InstRW<[GenericWriteFPULoad], (instregex "^LD_[BHWD]$")>;
 def : InstRW<[GenericWriteFPULoad], (instrs LD_F16)>;
+
+// Atomic instructions
+
+// FIXME: Define `WriteAtomic` in the MipsSchedule.td and
+// attach it to the Atomic2OpsPostRA, AtomicCmpSwapPostRA, ...
+// classes. Then just define resources for the `WriteAtomic` in each
+// machine models.
+def GenericAtomic : ProcResource<1> { let BufferSize = 1; }
+def GenericWriteAtomic : SchedWriteRes<[GenericAtomic]> { let Latency = 2; }
+
+def : InstRW<[GenericWriteAtomic],
+    (instregex "^ATOMIC_SWAP_I(8|16|32|64)_POSTRA$")>;
+def : InstRW<[GenericWriteAtomic],
+    (instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>;
+def : InstRW<[GenericWriteAtomic],
+    (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND)_I(8|16|32|64)_POSTRA$")>;
 }