From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sat, 9 Dec 2017 19:56:39 +0000 (+0000)
Subject: [X86] Tag frame pointer XORs instruction scheduler classes
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=02825318ae1c042cfb0bffb7d5e44376ec152a97;p=llvm

[X86] Tag frame pointer XORs instruction scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320261 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index a897cef774f..a5b04c968da 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -147,9 +147,11 @@ def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),
 // frame register after register allocation.
 let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in {
   def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
-                  "xorl\t$$FP, $src", []>, Requires<[NotLP64]>;
+                  "xorl\t$$FP, $src", [], IIC_BIN_NONMEM>,
+                  Requires<[NotLP64]>, Sched<[WriteALU]>;
   def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
-                  "xorq\t$$FP $src", []>, Requires<[In64BitMode]>;
+                  "xorq\t$$FP $src", [], IIC_BIN_NONMEM>,
+                  Requires<[In64BitMode]>, Sched<[WriteALU]>;
 }
 
 //===----------------------------------------------------------------------===//