From: Simon Pilgrim Date: Wed, 12 Jun 2019 11:08:29 +0000 (+0000) Subject: [XCore] CombineSTORE - Use allowsMemoryAccess wrapper. NFCI. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0276d5159476102d247a31089ad5c868d76ced76;p=llvm [XCore] CombineSTORE - Use allowsMemoryAccess wrapper. NFCI. Noticed in D63075 - there was a allowsMisalignedMemoryAccesses call to check for unaligned loads and a check for aligned legal type loads - which is exactly what allowsMemoryAccess does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363141 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 2145ba5a6f8..072278d9fc4 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1778,11 +1778,10 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, break; case ISD::STORE: { // Replace unaligned store of unaligned load with memmove. - StoreSDNode *ST = cast(N); + StoreSDNode *ST = cast(N); if (!DCI.isBeforeLegalize() || - allowsMisalignedMemoryAccesses(ST->getMemoryVT(), - ST->getAddressSpace(), - ST->getAlignment()) || + allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), + ST->getMemoryVT(), *ST->getMemOperand()) || ST->isVolatile() || ST->isIndexed()) { break; } @@ -1791,12 +1790,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); assert((StoreBits % 8) == 0 && "Store size in bits must be a multiple of 8"); - unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment( - ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); unsigned Alignment = ST->getAlignment(); - if (Alignment >= ABIAlignment) { - break; - } if (LoadSDNode *LD = dyn_cast(ST->getValue())) { if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&