From: Mahavir Jain Date: Wed, 15 Aug 2018 15:22:39 +0000 (+0530) Subject: soc: fix trace memory region for single core mode X-Git-Tag: v3.2-beta1~291^2 X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=0075e2f316e627f9283c38ced996875ec07ff7a8;p=esp-idf soc: fix trace memory region for single core mode Signed-off-by: Mahavir Jain --- diff --git a/components/soc/esp32/soc_memory_layout.c b/components/soc/esp32/soc_memory_layout.c index e60fe83307..c6fa4635d2 100644 --- a/components/soc/esp32/soc_memory_layout.c +++ b/components/soc/esp32/soc_memory_layout.c @@ -156,9 +156,9 @@ SOC_RESERVE_MEMORY_REGION(0x3ffae000, 0x3ffae6e0, rom_data); #if CONFIG_MEMMAP_TRACEMEM #if CONFIG_MEMMAP_TRACEMEM_TWOBANKS -SOC_RESERVE_MEMORY_REGION(0x3fff8000, 0x40000000, trace_mem); //Reserve trace mem region +SOC_RESERVE_MEMORY_REGION(0x3fff8000, 0x40000000, trace_mem); //Reserve trace mem region, 32K for both cpu #else -SOC_RESERVE_MEMORY_REGION(0x3fff8000, 0x3fffc000, trace_mem); //Reserve trace mem region +SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace mem region, 16K (upper-half) for pro cpu #endif #endif