From: Diana Picus <diana.picus@linaro.org>
Date: Wed, 5 Jul 2017 11:32:12 +0000 (+0000)
Subject: [MachineIRBuilder] Add buildOr helper. NFC.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=004d5b661f855ea07f851c2faeffc07419a350e1;p=llvm

[MachineIRBuilder] Add buildOr helper. NFC.

This isn't used anywhere yet, but I need it for a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307141 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 72a21bf9fbd..46ef0af303d 100644
--- a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -296,6 +296,19 @@ public:
   MachineInstrBuilder buildAnd(unsigned Res, unsigned Op0,
                                unsigned Op1);
 
+  /// Build and insert \p Res<def> = G_OR \p Op0, \p Op1
+  ///
+  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
+  /// Op1.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
+  ///      with the same (scalar or vector) type).
+  ///
+  /// \return a MachineInstrBuilder for the newly created instruction.
+  MachineInstrBuilder buildOr(unsigned Res, unsigned Op0,
+                              unsigned Op1);
+
   /// Build and insert \p Res<def> = G_ANYEXT \p Op0
   ///
   /// G_ANYEXT produces a register of the specified width, with bits 0 to
diff --git a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index c0066f67ac6..9dcc63164b3 100644
--- a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -240,6 +240,10 @@ MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0,
   return buildBinaryOp(TargetOpcode::G_AND, Res, Op0, Op1);
 }
 
+MachineInstrBuilder MachineIRBuilder::buildOr(unsigned Res, unsigned Op0,
+                                               unsigned Op1) {
+  return buildBinaryOp(TargetOpcode::G_OR, Res, Op0, Op1);
+}
 
 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);