DbgValueHistoryCalculator: Ignore call instructions that claim to clobber SP.

The AArch64 backend marks calls that involve aggregate function
arguments as having an implicit def of SP. We already have the same
workaround in LiveDebugValues and in DbgValueHistoryCalculator for SP
clobbers in register masks. This adds register defs to the list.

Fixes rdar://problem/30361929 and Swift SR-3851.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304471 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp b/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
index 20e1467b30c3aeaf433e9d948ddd2c7807469d42..c2ad9db81cfd974fb166524aaad6404242f1f2bc 100644 (file)
--- a/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
+++ b/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
@@ -194,6 +194,10 @@ void llvm::calculateDbgValueHistory(const MachineFunction *MF,
         // some variables.
         for (const MachineOperand &MO : MI.operands()) {
           if (MO.isReg() && MO.isDef() && MO.getReg()) {
+            // Ignore call instructions that claim to clobber SP. The AArch64
+            // backend does this for aggregate function arguments.
+            if (MI.isCall() && MO.getReg() == SP)
+              continue;
             // If this is a virtual register, only clobber it since it doesn't
             // have aliases.
             if (TRI->isVirtualRegister(MO.getReg()))

diff --git a/test/DebugInfo/MIR/AArch64/clobber-sp.mir b/test/DebugInfo/MIR/AArch64/clobber-sp.mir
new file mode 100644 (file)
index 0000000..444faee
--- /dev/null
+++ b/test/DebugInfo/MIR/AArch64/clobber-sp.mir
@@ -0,0 +1,181 @@
+# RUN: llc -start-after=livedebugvalues -filetype=obj -o - %s \
+# RUN:   | llvm-dwarfdump - | FileCheck %s
+# CHECK: .debug_info contents:
+# CHECK: DW_TAG_formal_parameter
+# CHECK: DW_TAG_formal_parameter
+# CHECK-NEXT: DW_AT_location [DW_FORM_data4]   ([[LOC:.*]])
+# CHECK-NEXT: DW_AT_name {{.*}}"y"
+# CHECK: .debug_loc contents:
+# CHECK: [[LOC]]:
+# CHECK-SAME:        Beginning address offset: 0x0000000000000000
+# CHECK-NEXT:          Ending address offset: 0x0000000000000014
+# CHECK-NEXT:           Location description: 51
+#                                              reg1
+#
+# The range of y's [SP+8] location must not be interrupted by the call to h.
+# CHECK:            Beginning address offset: 0x0000000000000014
+# CHECK-NEXT:          Ending address offset: 0x0000000000000038
+# CHECK-NEXT:           Location description: 8f 08
+#                                              breg31 +8
+--- |
+  ; Generated at -Os from:
+  ;   struct Rect {
+  ;     double x, y, w, h;
+  ;   };
+  ;   void g(struct Rect);
+  ;   void h(int *);
+  ;   int f(int x, int y, struct Rect s) {
+  ;     g(s);
+  ;     if (y)
+  ;       h(&x);
+  ;     return 0;
+  ;   }
+  source_filename = "/tmp/clobber.c"
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "arm64-apple-ios"
+  
+  %struct.Rect = type { double, double, double, double }
+  
+  ; Function Attrs: nounwind optsize ssp
+  define i32 @f(i32 %x, i32 %y, [4 x double] %s.coerce) local_unnamed_addr #0 !dbg !7 {
+  entry:
+    %x.addr = alloca i32, align 4
+    tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !19, metadata !22), !dbg !23
+    store i32 %x, i32* %x.addr, align 4, !tbaa !24
+    tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !20, metadata !22), !dbg !28
+    tail call void @llvm.dbg.declare(metadata %struct.Rect* undef, metadata !21, metadata !22), !dbg !29
+    tail call void @g([4 x double] %s.coerce) #4, !dbg !30
+    %tobool = icmp eq i32 %y, 0, !dbg !31
+    br i1 %tobool, label %if.end, label %if.then, !dbg !33
+  
+  if.then:                                          ; preds = %entry
+    tail call void @llvm.dbg.value(metadata i32* %x.addr, i64 0, metadata !19, metadata !22), !dbg !23
+    call void @h(i32* nonnull %x.addr) #4, !dbg !34
+    br label %if.end, !dbg !34
+  
+  if.end:                                           ; preds = %if.then, %entry
+    ret i32 0, !dbg !35
+  }
+  
+  declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+  declare void @g([4 x double]) local_unnamed_addr #2
+  declare void @h(i32*) local_unnamed_addr #2
+  declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+  declare void @llvm.stackprotector(i8*, i8**) #3
+  
+  attributes #0 = { nounwind optsize ssp }
+  attributes #1 = { nounwind readnone speculatable }
+  attributes #2 = { optsize }
+  attributes #3 = { nounwind }
+  attributes #4 = { nounwind optsize }
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5}
+  !llvm.ident = !{!6}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 5.0.0 (trunk 302682) (llvm/trunk 302683)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "/tmp/clobber.c", directory: "/Volumes/Data/apple-internal/swift")
+  !2 = !{}
+  !3 = !{i32 2, !"Dwarf Version", i32 2}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"PIC Level", i32 2}
+  !6 = !{!"clang version 5.0.0 (trunk 302682) (llvm/trunk 302683)"}
+  !7 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 7, type: !8, isLocal: false, isDefinition: true, scopeLine: 7, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !18)
+  !8 = !DISubroutineType(types: !9)
+  !9 = !{!10, !10, !10, !11}
+  !10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !11 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Rect", file: !1, line: 1, size: 256, elements: !12)
+  !12 = !{!13, !15, !16, !17}
+  !13 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !11, file: !1, line: 2, baseType: !14, size: 64)
+  !14 = !DIBasicType(name: "double", size: 64, encoding: DW_ATE_float)
+  !15 = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: !11, file: !1, line: 2, baseType: !14, size: 64, offset: 64)
+  !16 = !DIDerivedType(tag: DW_TAG_member, name: "w", scope: !11, file: !1, line: 2, baseType: !14, size: 64, offset: 128)
+  !17 = !DIDerivedType(tag: DW_TAG_member, name: "h", scope: !11, file: !1, line: 2, baseType: !14, size: 64, offset: 192)
+  !18 = !{!19, !20, !21}
+  !19 = !DILocalVariable(name: "x", arg: 1, scope: !7, file: !1, line: 7, type: !10)
+  !20 = !DILocalVariable(name: "y", arg: 2, scope: !7, file: !1, line: 7, type: !10)
+  !21 = !DILocalVariable(name: "s", arg: 3, scope: !7, file: !1, line: 7, type: !11)
+  !22 = !DIExpression()
+  !23 = !DILocation(line: 7, column: 11, scope: !7)
+  !24 = !{!25, !25, i64 0}
+  !25 = !{!"int", !26, i64 0}
+  !26 = !{!"omnipotent char", !27, i64 0}
+  !27 = !{!"Simple C/C++ TBAA"}
+  !28 = !DILocation(line: 7, column: 18, scope: !7)
+  !29 = !DILocation(line: 7, column: 33, scope: !7)
+  !30 = !DILocation(line: 8, column: 3, scope: !7)
+  !31 = !DILocation(line: 9, column: 7, scope: !32)
+  !32 = distinct !DILexicalBlock(scope: !7, file: !1, line: 9, column: 7)
+  !33 = !DILocation(line: 9, column: 7, scope: !7)
+  !34 = !DILocation(line: 10, column: 5, scope: !32)
+  !35 = !DILocation(line: 12, column: 3, scope: !7)
+
+...
+---
+name:            f
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:         
+  - { reg: '%w0' }
+  - { reg: '%w1' }
+  - { reg: '%d0' }
+  - { reg: '%d1' }
+  - { reg: '%d2' }
+  - { reg: '%d3' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       32
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+stack:           
+  - { id: 0, name: x.addr, offset: -20, size: 4, alignment: 4, local-offset: -4 }
+  - { id: 1, type: spill-slot, offset: -24, size: 4, alignment: 4 }
+  - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%lr' }
+  - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp' }
+body:             |
+  bb.0.entry:
+    successors: %bb.2.if.end(0x40000000), %bb.1.if.then(0x40000000)
+    liveins: %w0, %w1, %d0, %d1, %d2, %d3, %lr
+  
+    %sp = frame-setup SUBXri %sp, 32, 0
+    frame-setup STPXi killed %fp, killed %lr, %sp, 2 :: (store 8 into %stack.3), (store 8 into %stack.2)
+    %fp = frame-setup ADDXri %sp, 16, 0
+    DBG_VALUE debug-use %w0, debug-use _, !19, !22, debug-location !23
+    STURWi killed %w0, %fp, -4 :: (store 4 into %stack.0.x.addr)
+    DBG_VALUE debug-use %w1, debug-use _, !20, !22, debug-location !28
+    STRWui killed %w1, %sp, 2, debug-location !30 :: (store 4 into %stack.1)
+    DBG_VALUE %sp, 8, !20, !22, debug-location !28
+    BL @g, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %d0, implicit killed %d1, implicit killed %d2, implicit killed %d3, implicit-def %sp, debug-location !30
+    %w0 = LDRWui %sp, 2, debug-location !33 :: (load 4 from %stack.1)
+    CBZW killed %w0, %bb.2.if.end, debug-location !33
+  
+  bb.1.if.then:
+    successors: %bb.2.if.end(0x80000000)
+  
+    DBG_VALUE debug-use %sp, 8, !20, !22, debug-location !28
+    %x0 = SUBXri %fp, 4, 0
+    DBG_VALUE debug-use %x0, debug-use _, !19, !22, debug-location !23
+    BL @h, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %x0, debug-location !34
+  
+  bb.2.if.end:
+    DBG_VALUE debug-use %sp, 8, !20, !22, debug-location !28
+    %w8 = MOVZWi 0, 0
+    %x0 = ORRXrs %xzr, undef %x8, 0, implicit killed %w8, debug-location !35
+    %fp, %lr = LDPXi %sp, 2, debug-location !35 :: (load 8 from %stack.3), (load 8 from %stack.2)
+    %sp = ADDXri %sp, 32, 0, debug-location !35
+    RET undef %lr, implicit killed %w0, debug-location !35
+
+...

diff --git a/test/DebugInfo/MIR/AArch64/lit.local.cfg b/test/DebugInfo/MIR/AArch64/lit.local.cfg
new file mode 100644 (file)
index 0000000..cec29af
--- /dev/null
+++ b/test/DebugInfo/MIR/AArch64/lit.local.cfg
@@ -0,0 +1,3 @@
+if not 'AArch64' in config.root.targets:
+    config.unsupported = True
+