Revert "Correct register pressure calculation in presence of subregs"

This reverts commit r296009. It broke one out of tree target and also
does not account for all partial lines added or removed when calculating
PressureDiff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296182 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/RegisterPressure.h b/include/llvm/CodeGen/RegisterPressure.h
index 23fab7b0684ac77cc96293870f4c139140aa12c2..a3ea41d5236e3be47d39ba9d2d82b26617552cf6 100644 (file)
--- a/include/llvm/CodeGen/RegisterPressure.h
+++ b/include/llvm/CodeGen/RegisterPressure.h
@@ -156,7 +156,7 @@ public:
   const_iterator begin() const { return &PressureChanges[0]; }
   const_iterator end() const { return &PressureChanges[MaxPSets]; }
 
-  void addPressureChange(RegisterMaskPair P, bool IsDec,
+  void addPressureChange(unsigned RegUnit, bool IsDec,
                          const MachineRegisterInfo *MRI);
 
   void dump(const TargetRegisterInfo &TRI) const;

diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index 3ee5685123cf1501d715d55a7186ccac11154643..673cca7f44a905250fe01963224145a53e142389 100644 (file)
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -30,7 +30,6 @@ namespace llvm {
 
 class BitVector;
 class MachineFunction;
-class MachineRegisterInfo;
 class RegScavenger;
 template<class T> class SmallVectorImpl;
 class VirtRegMap;
@@ -720,12 +719,6 @@ public:
   /// Get the weight in units of pressure for this register unit.
   virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
 
-  /// Get the weight in units of pressure for a sub register of this register
-  /// unit given a lane mask.
-  virtual unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,
-                                    unsigned RegUnit,
-                                    LaneBitmask LaneMask) const;
-
   /// Get the number of dimensions of register pressure.
   virtual unsigned getNumRegPressureSets() const = 0;
 

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 066398358e8df870656d7bbb5b4f747b243eacf7..79b02c7de8c9fe079cad48fca1d1a6754c1ce61e 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -1085,7 +1085,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
           continue;
 
         PressureDiff &PDiff = getPressureDiff(&SU);
-        PDiff.addPressureChange(P, Decrement, &MRI);
+        PDiff.addPressureChange(Reg, Decrement, &MRI);
         DEBUG(
           dbgs() << "  UpdateRegP: SU(" << SU.NodeNum << ") "
                  << PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
@@ -1123,7 +1123,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
               LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
           if (LRQ.valueIn() == VNI) {
             PressureDiff &PDiff = getPressureDiff(SU);
-            PDiff.addPressureChange(P, true, &MRI);
+            PDiff.addPressureChange(Reg, true, &MRI);
             DEBUG(
               dbgs() << "  UpdateRegP: SU(" << SU->NodeNum << ") "
                      << *SU->getInstr();

diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp
index b22b36a3607f8efb3d5213885887a71999972a90..c726edc88b41c1de86eae0d4f2f3665c1162d428 100644 (file)
--- a/lib/CodeGen/RegisterPressure.cpp
+++ b/lib/CodeGen/RegisterPressure.cpp
@@ -46,29 +46,16 @@
 
 using namespace llvm;
 
-/// Clamp lane masks to maximum posible value.
-static void clampMasks(const MachineRegisterInfo &MRI, unsigned Reg,
-                       LaneBitmask& LaneMask1, LaneBitmask& LaneMask2) {
-  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
-    LaneBitmask Max = MRI.getMaxLaneMaskForVReg(Reg);
-    LaneMask1 &= Max;
-    LaneMask2 &= Max;
-  }
-}
-
 /// Increase pressure for each pressure set provided by TargetRegisterInfo.
 static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure,
                                 const MachineRegisterInfo &MRI, unsigned Reg,
                                 LaneBitmask PrevMask, LaneBitmask NewMask) {
   assert((PrevMask & ~NewMask).none() && "Must not remove bits");
-
-  clampMasks(MRI, Reg, PrevMask, NewMask);
-  if ((NewMask & ~PrevMask).none())
+  if (PrevMask.any() || NewMask.none())
     return;
 
-  const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
-  unsigned Weight = TRI->getRegUnitWeight(MRI, Reg, NewMask & ~PrevMask);
   PSetIterator PSetI = MRI.getPressureSets(Reg);
+  unsigned Weight = PSetI.getWeight();
   for (; PSetI.isValid(); ++PSetI)
     CurrSetPressure[*PSetI] += Weight;
 }
@@ -78,13 +65,11 @@ static void decreaseSetPressure(std::vector<unsigned> &CurrSetPressure,
                                 const MachineRegisterInfo &MRI, unsigned Reg,
                                 LaneBitmask PrevMask, LaneBitmask NewMask) {
   //assert((NewMask & !PrevMask) == 0 && "Must not add bits");
-  clampMasks(MRI, Reg, PrevMask, NewMask);
-  if ((~NewMask & PrevMask).none())
+  if (NewMask.any() || PrevMask.none())
     return;
 
-  const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
-  unsigned Weight = TRI->getRegUnitWeight(MRI, Reg, ~NewMask & PrevMask);
   PSetIterator PSetI = MRI.getPressureSets(Reg);
+  unsigned Weight = PSetI.getWeight();
   for (; PSetI.isValid(); ++PSetI) {
     assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");
     CurrSetPressure[*PSetI] -= Weight;
@@ -154,14 +139,11 @@ void PressureDiff::dump(const TargetRegisterInfo &TRI) const {
 void RegPressureTracker::increaseRegPressure(unsigned RegUnit,
                                              LaneBitmask PreviousMask,
                                              LaneBitmask NewMask) {
-  clampMasks(*MRI, RegUnit, PreviousMask, NewMask);
-  if ((NewMask & ~PreviousMask).none())
+  if (PreviousMask.any() || NewMask.none())
     return;
 
-  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
-  unsigned Weight = TRI->getRegUnitWeight(*MRI, RegUnit,
-                                          NewMask & ~PreviousMask);
   PSetIterator PSetI = MRI->getPressureSets(RegUnit);
+  unsigned Weight = PSetI.getWeight();
   for (; PSetI.isValid(); ++PSetI) {
     CurrSetPressure[*PSetI] += Weight;
     P.MaxSetPressure[*PSetI] =
@@ -662,19 +644,17 @@ void PressureDiffs::addInstruction(unsigned Idx,
   PressureDiff &PDiff = (*this)[Idx];
   assert(!PDiff.begin()->isValid() && "stale PDiff");
   for (const RegisterMaskPair &P : RegOpers.Defs)
-    PDiff.addPressureChange(P, true, &MRI);
+    PDiff.addPressureChange(P.RegUnit, true, &MRI);
 
   for (const RegisterMaskPair &P : RegOpers.Uses)
-    PDiff.addPressureChange(P, false, &MRI);
+    PDiff.addPressureChange(P.RegUnit, false, &MRI);
 }
 
 /// Add a change in pressure to the pressure diff of a given instruction.
-void PressureDiff::addPressureChange(RegisterMaskPair P, bool IsDec,
+void PressureDiff::addPressureChange(unsigned RegUnit, bool IsDec,
                                      const MachineRegisterInfo *MRI) {
-  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
-  int Weight = (int)TRI->getRegUnitWeight(*MRI, P.RegUnit, P.LaneMask);
-  PSetIterator PSetI = MRI->getPressureSets(P.RegUnit);
-  if (IsDec) Weight = -Weight;
+  PSetIterator PSetI = MRI->getPressureSets(RegUnit);
+  int Weight = IsDec ? -PSetI.getWeight() : PSetI.getWeight();
   for (; PSetI.isValid(); ++PSetI) {
     // Find an existing entry in the pressure diff for this PSet.
     PressureDiff::iterator I = nonconst_begin(), E = nonconst_end();

diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp
index 0d3f8eb6fb55f8c8ffd8a71646f567aeb45fea76..66cdad278e8daa9c80eb068451376266c94fc839 100644 (file)
--- a/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/lib/CodeGen/TargetRegisterInfo.cpp
@@ -412,15 +412,6 @@ bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
   return true;
 }
 
-/// Get the weight in units of pressure for a sub register of this register
-/// unit given a lane mask.
-unsigned TargetRegisterInfo::getRegUnitWeight(const MachineRegisterInfo &MRI,
-                                              unsigned RegUnit,
-                                              LaneBitmask LaneMask) const {
-  PSetIterator PSetI = MRI.getPressureSets(RegUnit);
-  return PSetI.getWeight();
-}
-
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD
 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,

diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp
index f1d037d1159578f38eda78d6c75ba668e2316af5..39324cbbcc02427a508be61d3607d3d70e2a0b27 100644 (file)
--- a/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -21,7 +21,6 @@
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/LLVMContext.h"
-#include "llvm/Support/MathExtras.h"
 
 using namespace llvm;
 
@@ -1409,18 +1408,3 @@ const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const {
     return Empty;
   return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit);
 }
-
-unsigned SIRegisterInfo::getRegUnitWeight(const MachineRegisterInfo &MRI,
-                                          unsigned RegUnit,
-                                          LaneBitmask LaneMask) const {
-  unsigned Weight = TargetRegisterInfo::getRegUnitWeight(MRI, RegUnit,
-                                                         LaneMask);
-  if (Weight > 1 && LaneMask.any() && !LaneMask.all() &&
-      isVirtualRegister(RegUnit)) {
-    LaneBitmask Max = MRI.getMaxLaneMaskForVReg(RegUnit);
-    if (Max != LaneMask && !Max.all() && !Max.none())
-      Weight = (Weight * countPopulation(LaneMask.getAsInteger())) /
-                         countPopulation(Max.getAsInteger());
-  }
-  return Weight;
-}

diff --git a/lib/Target/AMDGPU/SIRegisterInfo.h b/lib/Target/AMDGPU/SIRegisterInfo.h
index 258de19a17b0f71a22e9667f76089fa4ea0a1f75..679ed229758a0eef73f9e928942c43878d9e5706 100644 (file)
--- a/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -26,8 +26,6 @@ class SISubtarget;
 class SIMachineFunctionInfo;
 
 class SIRegisterInfo final : public AMDGPURegisterInfo {
-  using AMDGPUGenRegisterInfo::getRegUnitWeight;
-
 private:
   unsigned SGPRSetID;
   unsigned VGPRSetID;
@@ -230,10 +228,6 @@ public:
 
   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
 
-  unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,
-                            unsigned RegUnit,
-                            LaneBitmask LaneMask) const override;
-
 private:
   void buildSpillLoadStore(MachineBasicBlock::iterator MI,
                            unsigned LoadStoreOp,

diff --git a/test/CodeGen/AMDGPU/load-global-i32.ll b/test/CodeGen/AMDGPU/load-global-i32.ll
index b606b2555ca658dd56f67be08b553344db62f4ae..e3335347a63f1c4e7de563f54da98be8df74d058 100644 (file)
--- a/test/CodeGen/AMDGPU/load-global-i32.ll
+++ b/test/CodeGen/AMDGPU/load-global-i32.ll
@@ -424,25 +424,25 @@ define void @global_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; GCN-NOHSA: buffer_store_dwordx4
 ; GCN-NOHSA: buffer_store_dwordx4
 
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
 
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
 
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
 
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
-; GCN-HSA-DAG: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
+; GCN-HSA: flat_store_dwordx4
 
 define void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 {
   %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in

diff --git a/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir b/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir
deleted file mode 100644 (file)
index 0beb7b7..0000000
--- a/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir
+++ /dev/null
@@ -1,67 +0,0 @@
-# RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler -verify-misched %s -o - -debug-only=misched 2>&1 | FileCheck %s
-# REQUIRES: asserts
-
-# CHECK-LABEL: ScheduleDAGMILive::schedule starting
-
-# Check that def and use subregs count with the same weight
-# CHECK: %vreg9:sub1<def> = V_MUL_LO_I32 %vreg6:sub1, 3
-# CHECK: Pressure Diff : {{$}}
-
-# Check that a subreg does not count as a whole superreg
-# CHECK: %vreg9:sub0<def> = V_MUL_LO_I32 %vreg6:sub0, %vreg9:sub1
-# CHECK: Pressure Diff : VGPR_32 1{{$}}
-
-# Check that two subregs of the same register count as a whole register
-# CHECK: DS_WRITE2_B32 %vreg7, %vreg9:sub0, %vreg9:sub1
-# CHECK: Pressure Diff : VGPR_32 3{{$}}
-
----
-name:            mo_pset
-alignment:       0
-exposesReturnsTwice: false
-legalized:       false
-regBankSelected: false
-selected:        false
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: sreg_128 }
-  - { id: 1, class: sgpr_64 }
-  - { id: 2, class: sreg_32_xm0 }
-  - { id: 3, class: sgpr_32 }
-  - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_32_xm0_xexec }
-  - { id: 6, class: vreg_64 }
-  - { id: 7, class: vgpr_32 }
-  - { id: 8, class: vgpr_32 }
-  - { id: 9, class: vreg_64 }
-liveins:
-  - { reg: '%sgpr4_sgpr5', virtual-reg: '%1' }
-frameInfo:
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0:
-    liveins: %sgpr4_sgpr5
-
-    %1 = COPY %sgpr4_sgpr5
-    %5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
-    %m0 = S_MOV_B32 -1
-    %7 = COPY %5
-    %6 = DS_READ2_B32 %7, 0, 1, 0, implicit %m0, implicit %exec
-    undef %9.sub1 = V_MUL_LO_I32 %6.sub1, 3, implicit %exec
-    %9.sub0 = V_MUL_LO_I32 %6.sub0, %9.sub1, implicit %exec
-    DS_WRITE2_B32 %7, %9.sub0, %9.sub1, 4, 5, 0, implicit killed %m0, implicit %exec
-    S_ENDPGM
-
-...