]> granicus.if.org Git - llvm/commitdiff
[SelectionDAG] Use the inlined APInt shift methods since we've already bounds checked...
authorCraig Topper <craig.topper@intel.com>
Sun, 3 Dec 2017 03:07:09 +0000 (03:07 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 3 Dec 2017 03:07:09 +0000 (03:07 +0000)
The version that takes APInt is out of line. The 'unsigned' version optimizes for the common case of single word APInts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319628 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

index b456b74abd3de5ccfe8726cdff48b42360865964..0b59af2fa108729405e09743eecf3621df301738 100644 (file)
@@ -2463,27 +2463,30 @@ void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known,
   case ISD::SHL:
     if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
       computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
-      Known.Zero <<= *ShAmt;
-      Known.One <<= *ShAmt;
+      unsigned Shift = ShAmt->getZExtValue();
+      Known.Zero <<= Shift;
+      Known.One <<= Shift;
       // Low bits are known zero.
-      Known.Zero.setLowBits(ShAmt->getZExtValue());
+      Known.Zero.setLowBits(Shift);
     }
     break;
   case ISD::SRL:
     if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
       computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
-      Known.Zero.lshrInPlace(*ShAmt);
-      Known.One.lshrInPlace(*ShAmt);
+      unsigned Shift = ShAmt->getZExtValue();
+      Known.Zero.lshrInPlace(Shift);
+      Known.One.lshrInPlace(Shift);
       // High bits are known zero.
-      Known.Zero.setHighBits(ShAmt->getZExtValue());
+      Known.Zero.setHighBits(Shift);
     }
     break;
   case ISD::SRA:
     if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
       computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
+      unsigned Shift = ShAmt->getZExtValue();
       // Sign extend known zero/one bit (else is unknown).
-      Known.Zero.ashrInPlace(*ShAmt);
-      Known.One.ashrInPlace(*ShAmt);
+      Known.Zero.ashrInPlace(Shift);
+      Known.One.ashrInPlace(Shift);
     }
     break;
   case ISD::SIGN_EXTEND_INREG: {