Dport accesses would re-enable interrupts unconditionally, breaking things when calle...

diff --git a/components/esp32/dport_access.c b/components/esp32/dport_access.c
index 65b68f6e61c7001e6c46667d2fee4c5e3485b8f5..aa4bdbea0a022f585c305f90f315992f715f7b05 100644 (file)
--- a/components/esp32/dport_access.c
+++ b/components/esp32/dport_access.c
@@ -60,6 +60,10 @@ static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_N
 static uint32_t ccount_margin_cnt;
 #endif
 
+#ifndef CONFIG_FREERTOS_UNICORE
+static BaseType_t oldInterruptLevel[2];
+#endif
+
 /* stall other cpu that this cpu is pending to access dport register start */
 void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
 {
@@ -74,8 +78,8 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
 #ifdef DPORT_ACCESS_BENCHMARK
     ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
 #endif
-
-    portDISABLE_INTERRUPTS();
+    BaseType_t intLvl=portENTER_CRITICAL_NESTED();
+    oldInterruptLevel[cpu_id]=intLvl;
 
     if (dport_access_ref[cpu_id] == 0) {
         portENTER_CRITICAL_ISR(&g_dport_mux); 
@@ -121,7 +125,7 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
         portEXIT_CRITICAL_ISR(&g_dport_mux);
     }
         
-    portENABLE_INTERRUPTS();
+    portEXIT_CRITICAL_NESTED(oldInterruptLevel[cpu_id]);
 
 #ifdef DPORT_ACCESS_BENCHMARK
     ccount_end[cpu_id] = XTHAL_GET_CCOUNT();