[mips][ias] Further relax operands of certain assembly instructions

This patch adjusts the most relaxed predicate of immediate operands to accept
immediate forms such as ~(0xf0000000|0x000f00000). Previously these forms
would be accepted by GAS and rejected by IAS.

This partially resolves PR/30383.

Thanks to Sean Bruno for reporting the issue!

Reviewers: slthakur, seanbruno

Differential Revision: https://reviews.llvm.org/D29218

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295965 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 3a83c05a429911e5a5ab7934fb2f77f3be0c1d4e..2a69860a0fedb054ede7d7f81f9d1a76ab24e93a 100644 (file)
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -2379,10 +2379,10 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
     return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::NORImm:
     return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
-  case Mips::ADDi:
-  case Mips::ADDiu:
-  case Mips::SLTi:
-  case Mips::SLTiu:
+  case Mips::ADDi:   case Mips::ADDi_MM:
+  case Mips::ADDiu:  case Mips::ADDiu_MM:
+  case Mips::SLTi:   case Mips::SLTi_MM:
+  case Mips::SLTiu:  case Mips::SLTiu_MM:
     if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
         Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
       int64_t ImmValue = Inst.getOperand(2).getImm();
@@ -2392,9 +2392,9 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                                          : MER_Success;
     }
     return MER_NotAMacro;
-  case Mips::ANDi:
-  case Mips::ORi:
-  case Mips::XORi:
+  case Mips::ANDi:  case Mips::ANDi_MM:
+  case Mips::ORi:   case Mips::ORi_MM:
+  case Mips::XORi:  case Mips::XORi_MM:
     if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
         Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
       int64_t ImmValue = Inst.getOperand(2).getImm();
@@ -3821,30 +3821,51 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
     switch (FinalOpcode) {
     default:
       llvm_unreachable("unimplemented expansion");
-    case (Mips::ADDi):
+    case Mips::ADDi:
       FinalOpcode = Mips::ADD;
       break;
-    case (Mips::ADDiu):
+    case Mips::ADDiu:
       FinalOpcode = Mips::ADDu;
       break;
-    case (Mips::ANDi):
+    case Mips::ANDi:
       FinalOpcode = Mips::AND;
       break;
-    case (Mips::NORImm):
+    case Mips::NORImm:
       FinalOpcode = Mips::NOR;
       break;
-    case (Mips::ORi):
+    case Mips::ORi:
       FinalOpcode = Mips::OR;
       break;
-    case (Mips::SLTi):
+    case Mips::SLTi:
       FinalOpcode = Mips::SLT;
       break;
-    case (Mips::SLTiu):
+    case Mips::SLTiu:
       FinalOpcode = Mips::SLTu;
       break;
-    case (Mips::XORi):
+    case Mips::XORi:
       FinalOpcode = Mips::XOR;
       break;
+    case Mips::ADDi_MM:
+      FinalOpcode = Mips::ADD_MM;
+      break;
+    case Mips::ADDiu_MM:
+      FinalOpcode = Mips::ADDu_MM;
+      break;
+    case Mips::ANDi_MM:
+      FinalOpcode = Mips::AND_MM;
+      break;
+    case Mips::ORi_MM:
+      FinalOpcode = Mips::OR_MM;
+      break;
+    case Mips::SLTi_MM:
+      FinalOpcode = Mips::SLT_MM;
+      break;
+    case Mips::SLTiu_MM:
+      FinalOpcode = Mips::SLTu_MM;
+      break;
+    case Mips::XORi_MM:
+      FinalOpcode = Mips::XOR_MM;
+      break;
     }
 
     if (FinalDstReg == Mips::NoRegister)

diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td
index c0de9e7390a4cb5819d1a3fa451aad4312f21e67..ee554bc7f69a96ae4a4aaa22718bc59ee874129a 100644 (file)
--- a/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -1136,12 +1136,6 @@ let Predicates = [InMicroMips] in {
   def : MipsInstAlias<
           "sgtu $rs, $rt",
           (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
-  def : MipsInstAlias<"slt $rs, $rt, $imm",
-                      (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
-                               simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<"sltu $rs, $rt, $imm",
-                      (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
-                                simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<"sll $rd, $rt, $rs",
                       (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"sra $rd, $rt, $rs",
@@ -1163,18 +1157,21 @@ let Predicates = [InMicroMips] in {
   def : MipsInstAlias<"rotr $rt, $imm",
                       (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
   def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
-  def : MipsInstAlias<"and $rs, $rt, $imm",
-                      (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
-  def : MipsInstAlias<"and $rs, $imm",
-                      (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
-  def : MipsInstAlias<"or $rs, $rt, $imm",
-                      (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
-  def : MipsInstAlias<"or $rs, $imm",
-                      (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
-  def : MipsInstAlias<"xor $rs, $rt, $imm",
-                      (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
-  def : MipsInstAlias<"xor $rs, $imm",
-                      (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>;
+
   def : MipsInstAlias<"not $rt, $rs",
                       (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
   def : MipsInstAlias<"not $rt",

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index e946a953c0ac682004f56484b09697aaccc4eb6f..c84642773ae59a853119a21c2ab47e9e92a67c44 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -541,7 +541,7 @@ def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> {
 def SImm32RelaxedAsmOperandClass
     : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {
   let Name = "SImm32_Relaxed";
-  let PredicateMethod = "isAnyImm<32>";
+  let PredicateMethod = "isAnyImm<33>";
   let DiagnosticType = "SImm32_Relaxed";
 }
 def SImm32AsmOperandClass
@@ -2320,6 +2320,19 @@ def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
+
+multiclass OneOrTwoOperandMacroImmediateAlias<string Memnomic,
+                                         Instruction Opcode> {
+  def : MipsInstAlias<!strconcat(Memnomic, " $rs, $rt, $imm"),
+                                (Opcode GPR32Opnd:$rs,
+                                        GPR32Opnd:$rt,
+                                        simm32_relaxed:$imm), 0>;
+  def : MipsInstAlias<!strconcat(Memnomic, " $rs, $imm"),
+                                (Opcode GPR32Opnd:$rs,
+                                        GPR32Opnd:$rs,
+                                        simm32_relaxed:$imm), 0>;
+}
+
 def : MipsInstAlias<"move $dst, $src",
                     (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
       GPR_32 {
@@ -2332,26 +2345,7 @@ def : MipsInstAlias<"move $dst, $src",
 }
 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
       ISA_MIPS1_NOT_32R6_64R6;
-def : MipsInstAlias<
-          "addu $rs, $rt, $imm",
-          (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
-def : MipsInstAlias<
-          "addu $rs, $imm",
-          (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
-def : MipsInstAlias<
-          "add $rs, $rt, $imm",
-          (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>,
-          ISA_MIPS1_NOT_32R6_64R6;
-def : MipsInstAlias<
-          "add $rs, $imm",
-          (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>,
-          ISA_MIPS1_NOT_32R6_64R6;
-def : MipsInstAlias<
-          "and $rs, $rt, $imm",
-          (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
-def : MipsInstAlias<
-          "and $rs, $imm",
-          (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
+
 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
 let Predicates = [NotInMicroMips] in {
 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
@@ -2378,30 +2372,6 @@ let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<
           "sgtu $$rs, $rt",
           (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
-  def : MipsInstAlias<
-          "slt $rs, $rt, $imm",
-          (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<
-          "sltu $rt, $rs, $imm",
-          (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<
-          "and $rs, $rt, $imm",
-          (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<
-          "and $rs, $imm",
-          (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<
-          "xor $rs, $rt, $imm",
-          (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<
-          "xor $rs, $imm",
-          (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<
-          "or $rs, $rt, $imm",
-          (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
-  def : MipsInstAlias<
-          "or $rs, $imm",
-          (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "not $rt, $rs",
           (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
@@ -2409,6 +2379,20 @@ let AdditionalPredicates = [NotInMicroMips] in {
           "not $rt",
           (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
   def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>;
+
+  defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>;
 }
 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
@@ -2517,8 +2501,10 @@ def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
                       "jal\t$rs"> ;
 
 def NORImm : MipsAsmPseudoInst<
-                 (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm),
-                 "nor\t$rs, $rt, $imm"> ;
+                 (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm),
+                 "nor\t$rs, $rt, $imm">;
+def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs,
+                                              simm32_relaxed:$imm)>;
 
 let hasDelaySlot = 1, isCTI = 1 in {
 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),

diff --git a/test/MC/Mips/instalias-imm-expanding.s b/test/MC/Mips/instalias-imm-expanding.s
index 9759dabdc0875268644facfe93da2bab6d1007bb..b26863169f0045906bd41cae54973da93686dee4 100644 (file)
--- a/test/MC/Mips/instalias-imm-expanding.s
+++ b/test/MC/Mips/instalias-imm-expanding.s
@@ -23,6 +23,10 @@ text_label:
 # CHECK: add    $4, $4, $1              # encoding: [0x20,0x20,0x81,0x00]
   add $4, 0xFFFFFFFF
 # CHECK: addi   $4, $4, -1              # encoding: [0xff,0xff,0x84,0x20]
+  add $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $1, 255                 # encoding: [0xff,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 65295           # encoding: [0x0f,0xff,0x21,0x34]
+# CHECK: add    $5, $5, $1              # encoding: [0x20,0x28,0xa1,0x00]
 
   add $4, $5, -0x80000000
 # CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
@@ -43,6 +47,10 @@ text_label:
 # CHECK: add    $4, $4, $5              # encoding: [0x20,0x20,0x85,0x00]
   add $4, $5, 0xFFFFFFFF
 # CHECK: addi   $4, $5, -1              # encoding: [0xff,0xff,0xa4,0x20]
+  add $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $4, 255                 # encoding: [0xff,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 65295           # encoding: [0x0f,0xff,0x84,0x34]
+# CHECK: add    $4, $4, $5              # encoding: [0x20,0x20,0x85,0x00]
 
   addu $4, -0x80000000
 # CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
@@ -63,6 +71,10 @@ text_label:
 # CHECK: addu   $4, $4, $1              # encoding: [0x21,0x20,0x81,0x00]
   addu $4, 0xFFFFFFFF
 # CHECK: addiu  $4, $4, -1              # encoding: [0xff,0xff,0x84,0x24]
+  addu $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $1, 255                 # encoding: [0xff,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 65295           # encoding: [0x0f,0xff,0x21,0x34]
+# CHECK: addu    $5, $5, $1              # encoding: [0x21,0x28,0xa1,0x00]
 
   addu $4, $5, -0x80000000
 # CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
@@ -83,6 +95,10 @@ text_label:
 # CHECK: addu   $4, $4, $5              # encoding: [0x21,0x20,0x85,0x00]
   addu $4, $5, 0xFFFFFFFF
 # CHECK: addiu  $4, $5, -1              # encoding: [0xff,0xff,0xa4,0x24]
+  addu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $4, 255                 # encoding: [0xff,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 65295           # encoding: [0x0f,0xff,0x84,0x34]
+# CHECK: addu    $4, $4, $5              # encoding: [0x21,0x20,0x85,0x00]
 
   and $4, -0x80000000
 # CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
@@ -103,6 +119,10 @@ text_label:
   and $4, 0xFFFFFFFF
 # CHECK: addiu  $1, $zero, -1           # encoding: [0xff,0xff,0x01,0x24]
 # CHECK: and    $4, $4, $1              # encoding: [0x24,0x20,0x81,0x00]
+  and $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $1, 255                 # encoding: [0xff,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 65295           # encoding: [0x0f,0xff,0x21,0x34]
+# CHECK: and    $5, $5, $1              # encoding: [0x24,0x28,0xa1,0x00]
 
   and $4, $5, -0x80000000
 # CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
@@ -123,6 +143,10 @@ text_label:
 # CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
   and $4, $5, 0xFFFFFFFF
 # CHECK: addiu  $4, $zero, -1           # encoding: [0xff,0xff,0x04,0x24]
+# CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
+  and $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $4, 255                 # encoding: [0xff,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 65295           # encoding: [0x0f,0xff,0x84,0x34]
 # CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
 
   nor $4, $5, 0
@@ -144,6 +168,34 @@ text_label:
 # CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
 # CHECK: ori    $4, $4, 42405           # encoding: [0xa5,0xa5,0x84,0x34]
 # CHECK: nor    $4, $4, $5              # encoding: [0x27,0x20,0x85,0x00]
+  nor $4, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $1, 255                 # encoding: [0xff,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 65295           # encoding: [0x0f,0xff,0x21,0x34]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
+
+  nor $4, 0
+# CHECK: addiu  $1, $zero, 0            # encoding: [0x00,0x00,0x01,0x24]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
+  nor $4, 1
+# CHECK: addiu  $1, $zero, 1            # encoding: [0x01,0x00,0x01,0x24]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
+  nor $4, 0x8000
+# CHECK: ori    $1, $zero, 32768        # encoding: [0x00,0x80,0x01,0x34]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
+  nor $4, -0x8000
+# CHECK: addiu  $1, $zero, -32768       # encoding: [0x00,0x80,0x01,0x24]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
+  nor $4, 0x10000
+# CHECK: lui    $1, 1                   # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
+  nor $4, 0x1a5a5
+# CHECK: lui    $1, 1                   # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 42405           # encoding: [0xa5,0xa5,0x21,0x34]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
+  nor $4, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $1, 255                 # encoding: [0xff,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 65295           # encoding: [0x0f,0xff,0x21,0x34]
+# CHECK: nor    $4, $4, $1              # encoding: [0x27,0x20,0x81,0x00]
 
   or $4, -0x80000000
 # CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
@@ -165,6 +217,10 @@ text_label:
   or $4, 0xFFFFFFFF
 # CHECK: addiu  $1, $zero, -1           # encoding: [0xff,0xff,0x01,0x24]
 # CHECK: or     $4, $4, $1              # encoding: [0x25,0x20,0x81,0x00]
+  or $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $1, 255                 # encoding: [0xff,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 65295           # encoding: [0x0f,0xff,0x21,0x34]
+# CHECK: or     $5, $5, $1              # encoding: [0x25,0x28,0xa1,0x00]
 
   or $4, $5, -0x80000000
 # CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
@@ -185,6 +241,10 @@ text_label:
 # CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
   or $4, $5, 0xFFFFFFFF
 # CHECK: addiu  $4, $zero, -1           # encoding: [0xff,0xff,0x04,0x24]
+# CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
+  or $4, $5, ~(0xF0000000|0x0F000000|0x000000F0)
+# CHECK: lui    $4, 255                 # encoding: [0xff,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 65295           # encoding: [0x0f,0xff,0x84,0x34]
 # CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
 
   slt $4, $5, -0x80000000
@@ -205,6 +265,10 @@ text_label:
 # CHECK: slt    $4, $4, $5              # encoding: [0x2a,0x20,0x85,0x00]
   slt $4, $5, 0xFFFFFFFF
 # CHECK: slti   $4, $5, -1              # encoding: [0xff,0xff,0xa4,0x28]
+  slt $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $4, 255                 # encoding: [0xff,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 65295           # encoding: [0x0f,0xff,0x84,0x34]
+# CHECK: slt    $4, $4, $5              # encoding: [0x2a,0x20,0x85,0x00]
 
   sltu $4, $5, -0x80000000
 # CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
@@ -224,6 +288,10 @@ text_label:
 # CHECK: sltu   $4, $4, $5              # encoding: [0x2b,0x20,0x85,0x00]
   sltu $4, $5, 0xFFFFFFFF
 # CHECK: sltiu  $4, $5, -1              # encoding: [0xff,0xff,0xa4,0x2c]
+  sltu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $4, 255                 # encoding: [0xff,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 65295           # encoding: [0x0f,0xff,0x84,0x34]
+# CHECK: sltu   $4, $4, $5              # encoding: [0x2b,0x20,0x85,0x00]
 
   xor $4, -0x80000000
 # CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
@@ -243,6 +311,10 @@ text_label:
 # CHECK: xor    $4, $4, $1              # encoding: [0x26,0x20,0x81,0x00]
   xor $4, 0xFFFFFFFF
 # CHECK: addiu  $1, $zero, -1           # encoding: [0xff,0xff,0x01,0x24]
+# CHECK: xor    $4, $4, $1              # encoding: [0x26,0x20,0x81,0x00]
+  xor $4, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $1, 255                 # encoding: [0xff,0x00,0x01,0x3c]
+# CHECK: ori    $1, $1, 65295           # encoding: [0x0f,0xff,0x21,0x34]
 # CHECK: xor    $4, $4, $1              # encoding: [0x26,0x20,0x81,0x00]
 
   xor $4, $5, -0x80000000
@@ -254,7 +326,7 @@ text_label:
 # CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
   xor $4, $5, -0x8000
 # CHECK: addiu  $4, $zero, -32768       # encoding: [0x00,0x80,0x04,0x24]
-# CHECK: xor $4, $4, $5                 # encoding: [0x26,0x20,0x85,0x00]
+# CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
   xor $4, $5, 0
 # CHECK: xori   $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x38]
   xor $4, $5, 0xFFFF
@@ -264,4 +336,8 @@ text_label:
 # CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
   xor $4, $5, 0xFFFFFFFF
 # CHECK: addiu  $4, $zero, -1           # encoding: [0xff,0xff,0x04,0x24]
+# CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
+  xor $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
+# CHECK: lui    $4, 255                 # encoding: [0xff,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 65295           # encoding: [0x0f,0xff,0x84,0x34]
 # CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]