[X86] Split immediate shifts tests. NFCI.

A future patch will combine logical shifts more aggressively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350396 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/avx512-shift.ll b/test/CodeGen/X86/avx512-shift.ll
index eda27c21adfe2d49fb4b67f552baeee8177d33c6..8cf08b852892a0ccb1da6a612ee02de4393d172d 100644 (file)
--- a/test/CodeGen/X86/avx512-shift.ll
+++ b/test/CodeGen/X86/avx512-shift.ll
@@ -1,52 +1,93 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=KNL
-;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefixes=CHECK,KNL
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefixes=CHECK,SKX
 
-define <16 x i32> @shift_16_i32(<16 x i32> %a) {
-; CHECK-LABEL: shift_16_i32:
+define <16 x i32> @ashr_16_i32(<16 x i32> %a) {
+; CHECK-LABEL: ashr_16_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpsrld $1, %zmm0, %zmm0
-; CHECK-NEXT:    vpslld $12, %zmm0, %zmm0
 ; CHECK-NEXT:    vpsrad $12, %zmm0, %zmm0
+; CHECK-NEXT:    retq
+   %b = ashr <16 x i32> %a, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
+   ret <16 x i32> %b
+}
+
+define <16 x i32> @lshr_16_i32(<16 x i32> %a) {
+; CHECK-LABEL: lshr_16_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpsrld $1, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
    %b = lshr <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
-   %c = shl <16 x i32> %b, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
-   %d = ashr <16 x i32> %c, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
-   ret <16 x i32> %d;
+   ret <16 x i32> %b
 }
 
-define <8 x i64> @shift_8_i64(<8 x i64> %a) {
-; CHECK-LABEL: shift_8_i64:
+define <16 x i32> @shl_16_i32(<16 x i32> %a) {
+; CHECK-LABEL: shl_16_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpslld $12, %zmm0, %zmm0
+; CHECK-NEXT:    retq
+   %b = shl <16 x i32> %a, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
+   ret <16 x i32> %b
+}
+
+define <8 x i64> @ashr_8_i64(<8 x i64> %a) {
+; CHECK-LABEL: ashr_8_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpsrlq $1, %zmm0, %zmm0
-; CHECK-NEXT:    vpsllq $12, %zmm0, %zmm0
 ; CHECK-NEXT:    vpsraq $12, %zmm0, %zmm0
+; CHECK-NEXT:    retq
+   %b = ashr <8 x i64> %a, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
+   ret <8 x i64> %b
+}
+
+define <8 x i64> @lshr_8_i64(<8 x i64> %a) {
+; CHECK-LABEL: lshr_8_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpsrlq $1, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
    %b = lshr <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
-   %c = shl <8 x i64> %b,  <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
-   %d = ashr <8 x i64> %c, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
-   ret <8 x i64> %d;
+   ret <8 x i64> %b
+}
+
+define <8 x i64> @shl_8_i64(<8 x i64> %a) {
+; CHECK-LABEL: shl_8_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpsllq $12, %zmm0, %zmm0
+; CHECK-NEXT:    retq
+   %b = shl <8 x i64> %a, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
+   ret <8 x i64> %b
 }
 
-define <4 x i64> @shift_4_i64(<4 x i64> %a) {
-; KNL-LABEL: shift_4_i64:
+define <4 x i64> @ashr_4_i64(<4 x i64> %a) {
+; KNL-LABEL: ashr_4_i64:
 ; KNL:       # %bb.0:
-; KNL-NEXT:    vpsrlq $1, %ymm0, %ymm0
-; KNL-NEXT:    vpsllq $12, %ymm0, %ymm0
+; KNL-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
 ; KNL-NEXT:    vpsraq $12, %zmm0, %zmm0
 ; KNL-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
 ; KNL-NEXT:    retq
 ;
-; SKX-LABEL: shift_4_i64:
+; SKX-LABEL: ashr_4_i64:
 ; SKX:       # %bb.0:
-; SKX-NEXT:    vpsrlq $1, %ymm0, %ymm0
-; SKX-NEXT:    vpsllq $12, %ymm0, %ymm0
 ; SKX-NEXT:    vpsraq $12, %ymm0, %ymm0
 ; SKX-NEXT:    retq
+   %b = ashr <4 x i64> %a, <i64 12, i64 12, i64 12, i64 12>
+   ret <4 x i64> %b
+}
+
+define <4 x i64> @lshr_4_i64(<4 x i64> %a) {
+; CHECK-LABEL: lshr_4_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpsrlq $1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
    %b = lshr <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
-   %c = shl <4 x i64> %b,  <i64 12, i64 12, i64 12, i64 12>
-   %d = ashr <4 x i64> %c, <i64 12, i64 12, i64 12, i64 12>
-   ret <4 x i64> %d;
+   ret <4 x i64> %b
+}
+
+define <4 x i64> @shl_4_i64(<4 x i64> %a) {
+; CHECK-LABEL: shl_4_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpsllq $12, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+   %b = shl <4 x i64> %a,  <i64 12, i64 12, i64 12, i64 12>
+   ret <4 x i64> %b
 }
 
 define <8 x i64> @variable_shl4(<8 x i64> %x, <8 x i64> %y) {