[SDAG] Deal with deleted node in PromoteIntShiftOp

Deal with case that initial node is deleted during dag-combine leading
to an assertional failure in promoteIntShiftOp.

Fixes PR32420.

Reviewers: spatel, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31403

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298931 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5d37c5cb400a00e57ef79cd4c8179f1873b62288..2cd70ed19fa273ab7f0fade1b5cda38b904b8dbd 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1144,26 +1144,32 @@ SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
   if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
     assert(PVT != VT && "Don't know what type to promote to!");
 
+    DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG));
+
     bool Replace = false;
     SDValue N0 = Op.getOperand(0);
+    SDValue N1 = Op.getOperand(1);
     if (Opc == ISD::SRA)
       N0 = SExtPromoteOperand(N0, PVT);
     else if (Opc == ISD::SRL)
       N0 = ZExtPromoteOperand(N0, PVT);
     else
       N0 = PromoteOperand(N0, PVT, Replace);
+
     if (!N0.getNode())
       return SDValue();
 
+    SDLoc DL(Op);
+    SDValue RV =
+        DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
+
     AddToWorklist(N0.getNode());
     if (Replace)
       ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
 
-    DEBUG(dbgs() << "\nPromoting ";
-          Op.getNode()->dump(&DAG));
-    SDLoc DL(Op);
-    return DAG.getNode(ISD::TRUNCATE, DL, VT,
-                       DAG.getNode(Opc, DL, PVT, N0, Op.getOperand(1)));
+    // Deal with Op being deleted.
+    if (Op && Op.getOpcode() != ISD::DELETED_NODE)
+      return RV;
   }
   return SDValue();
 }

diff --git a/test/CodeGen/X86/pr32420.ll b/test/CodeGen/X86/pr32420.ll
new file mode 100644 (file)
index 0000000..bf3a472
--- /dev/null
+++ b/test/CodeGen/X86/pr32420.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.12.0"
+
+@a = common local_unnamed_addr global i16 0, align 4
+@b = common local_unnamed_addr global i16 0, align 4
+
+define i32 @PR32420() {
+; CHECK-LABEL: PR32420:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movq _a@{{.*}}(%rip), %rax
+; CHECK-NEXT:    movzwl (%rax), %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shll $12, %ecx
+; CHECK-NEXT:    sarw $12, %cx
+; CHECK-NEXT:    movq _b@{{.*}}(%rip), %rdx
+; CHECK-NEXT:    movw %cx, %si
+; CHECK-NEXT:    orw (%rdx), %si
+; CHECK-NEXT:    andl %ecx, %esi
+; CHECK-NEXT:    movw %si, (%rdx)
+; CHECK-NEXT:    retq
+  %load2 = load i16, i16* @a, align 4
+  %shl3 = shl i16 %load2, 12
+  %ashr4 = ashr i16 %shl3, 12
+  %t2 = load volatile i16, i16* @b, align 4
+  %conv8 = or i16 %t2, %ashr4
+  %load9 = load i16, i16* @a, align 4
+  %shl10 = shl i16 %load9, 12
+  %ashr11 = ashr i16 %shl10, 12
+  %and = and i16 %conv8, %ashr11
+  store i16 %and, i16* @b, align 4
+  %cast1629 = zext i16 %load2 to i32
+  ret i32 %cast1629
+}