[AMDGPU][MC][GFX10] Enabled decoding of 'null' operand

See bug 43485: https://bugs.llvm.org/show_bug.cgi?id=43485

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D68348

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373740 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 4ec4be9bc4858939ea38d86f40df1f1fea431648..e3b179c5caf40408f87652a7ceb4bbf428f987c4 100644 (file)
--- a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -1095,6 +1095,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
   case 106: return createRegOperand(VCC);
   case 108: return createRegOperand(TBA);
   case 110: return createRegOperand(TMA);
+  case 125: return createRegOperand(SGPR_NULL);
   case 126: return createRegOperand(EXEC);
   case 235: return createRegOperand(SRC_SHARED_BASE);
   case 236: return createRegOperand(SRC_SHARED_LIMIT);

diff --git a/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt b/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt
new file mode 100644 (file)
index 0000000..adeb47a
--- /dev/null
+++ b/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10
+
+# GFX10: s_ashr_i64 s[0:1], null, s0     ; encoding: [0x7d,0x00,0x80,0x91]
+0x7d,0x00,0x80,0x91
+
+# GFX10: s_and_b64 s[0:1], null, null    ; encoding: [0x7d,0x7d,0x80,0x87]
+0x7d,0x7d,0x80,0x87