[RISCV] Add basic RISCVAsmParser

This doesn't yet support parsing things like %pcrel_hi(foo), but will handle
basic instructions with register or immediate operands.

Differential Revision: https://reviews.llvm.org/D23563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310361 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/RISCV/CMakeLists.txt b/lib/Target/RISCV/CMakeLists.txt
index c8887548b9179a1fb28895eeb660b93d1bcede60..47e53a367220f9483af9a3c6ff739174f2fdede0 100644 (file)
--- a/lib/Target/RISCV/CMakeLists.txt
+++ b/lib/Target/RISCV/CMakeLists.txt
@@ -3,6 +3,7 @@ set(LLVM_TARGET_DEFINITIONS RISCV.td)
 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
+tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 
@@ -10,5 +11,6 @@ add_llvm_target(RISCVCodeGen
   RISCVTargetMachine.cpp
   )
 
+add_subdirectory(AsmParser)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)

diff --git a/lib/Target/RISCV/LLVMBuild.txt b/lib/Target/RISCV/LLVMBuild.txt
index 9ba5fec928f38a5f284b595fb57e1dce04d23170..3e5400489215661338236a461f0b802d23b9df3e 100644 (file)
--- a/lib/Target/RISCV/LLVMBuild.txt
+++ b/lib/Target/RISCV/LLVMBuild.txt
@@ -16,12 +16,13 @@
 ;===------------------------------------------------------------------------===;
 
 [common]
-subdirectories = TargetInfo MCTargetDesc
+subdirectories = AsmParser TargetInfo MCTargetDesc
 
 [component_0]
 type = TargetGroup
 name = RISCV
 parent = Target
+has_asmparser = 1
 
 [component_1]
 type = Library

diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td
index 14838309a1bfc423d321cfb7ad319758bbb854af..19e11839ac3a686d4189a437d910c3eacdbaed69 100644 (file)
--- a/lib/Target/RISCV/RISCV.td
+++ b/lib/Target/RISCV/RISCV.td
@@ -22,6 +22,11 @@ def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
+def RISCVAsmParser : AsmParser {
+  let ShouldEmitMatchRegisterAltName = 1;
+}
+
 def RISCV : Target {
   let InstructionSet = RISCVInstrInfo;
+  let AssemblyParsers = [RISCVAsmParser];
 }

diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td
index 52530c2f136cea914ba01a27abd9e685c9277e3a..93d13f79390eefcd66cffb1403c49f9056b37169 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/lib/Target/RISCV/RISCVInstrInfo.td
@@ -13,7 +13,16 @@
 
 include "RISCVInstrFormats.td"
 
-def simm12 : Operand<i32>;
+class SImmAsmOperand<int width>
+  : AsmOperandClass {
+  let Name = "SImm" # width;
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = !strconcat("Invalid", Name);
+}
+
+def simm12 : Operand<i32> {
+  let ParserMatchClass = SImmAsmOperand<12>;
+}
 
 // As noted in RISCVRegisterInfo.td, the hope is that support for
 // variable-sized register classes will mean that instruction definitions do