[GlobalISel][X86] Split select tests. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300666 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/GlobalISel/binop-isel.ll b/test/CodeGen/X86/GlobalISel/binop.ll
similarity index 100%
rename from test/CodeGen/X86/GlobalISel/binop-isel.ll
rename to test/CodeGen/X86/GlobalISel/binop.ll

diff --git a/test/CodeGen/X86/GlobalISel/legalize-const.mir b/test/CodeGen/X86/GlobalISel/legalize-constant.mir
similarity index 100%
rename from test/CodeGen/X86/GlobalISel/legalize-const.mir
rename to test/CodeGen/X86/GlobalISel/legalize-constant.mir

diff --git a/test/CodeGen/X86/GlobalISel/memop-isel.ll b/test/CodeGen/X86/GlobalISel/memop.ll
similarity index 100%
rename from test/CodeGen/X86/GlobalISel/memop-isel.ll
rename to test/CodeGen/X86/GlobalISel/memop.ll

diff --git a/test/CodeGen/X86/GlobalISel/select-add.mir b/test/CodeGen/X86/GlobalISel/select-add.mir
new file mode 100644 (file)
index 0000000..27fcc22
--- /dev/null
+++ b/test/CodeGen/X86/GlobalISel/select-add.mir
@@ -0,0 +1,226 @@
+# RUN: llc -mtriple=x86_64-linux-gnu                                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx                      -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+
+--- |
+  define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
+    %ret = add i64 %arg1, %arg2
+    ret i64 %ret
+  }
+
+  define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
+    %ret = add i32 %arg1, %arg2
+    ret i32 %ret
+  }
+
+  define float @test_add_float(float %arg1, float %arg2) {
+    %ret = fadd float %arg1, %arg2
+    ret float %ret
+  }
+
+  define double @test_add_double(double %arg1, double %arg2) {
+    %ret = fadd double %arg1, %arg2
+    ret double %ret
+  }
+
+  define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
+    %ret = add <4 x i32> %arg1, %arg2
+    ret <4 x i32> %ret
+  }
+
+  define <4 x float>  @test_add_v4f32(<4 x float> %arg1, <4 x float>  %arg2) {
+    %ret = fadd <4 x float>  %arg1, %arg2
+    ret <4 x float>  %ret
+  }
+...
+
+---
+name:            test_add_i64
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:  - { id: 0, class: gr64 }
+# ALL-NEXT:  - { id: 1, class: gr64 }
+# ALL-NEXT:  - { id: 2, class: gr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:      %0 = COPY %rdi
+# ALL-NEXT: %1 = COPY %rsi
+# ALL-NEXT: %2 = ADD64rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi, %esi
+
+    %0(s64) = COPY %rdi
+    %1(s64) = COPY %rsi
+    %2(s64) = G_ADD %0, %1
+    %rax = COPY %2(s64)
+
+...
+
+---
+name:            test_add_i32
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:  - { id: 0, class: gr32 }
+# ALL-NEXT:  - { id: 1, class: gr32 }
+# ALL-NEXT:  - { id: 2, class: gr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:      %0 = COPY %edi
+# ALL-NEXT: %1 = COPY %esi
+# ALL-NEXT: %2 = ADD32rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi, %esi
+
+    %0(s32) = COPY %edi
+    %1(s32) = COPY %esi
+    %2(s32) = G_ADD %0, %1
+    %rax = COPY %2(s32)
+
+...
+---
+name:            test_add_float
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512F-NEXT:  - { id: 0, class: fr32 }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr32 }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr32 }
+# AVX512ALL-NEXT:  - { id: 0, class: fr32x }
+# AVX512ALL-NEXT:  - { id: 1, class: fr32x }
+# AVX512ALL-NEXT:  - { id: 2, class: fr32x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %xmm0
+# ALL-NEXT:     %1 = COPY %xmm1
+# SSE-NEXT:     %2 = ADDSSrr %0, %1
+# AVX-NEXT:     %2 = VADDSSrr %0, %1
+# AVX512F-NEXT: %2 = VADDSSZrr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(s32) = COPY %xmm0
+    %1(s32) = COPY %xmm1
+    %2(s32) = G_FADD %0, %1
+    %xmm0 = COPY %2(s32)
+    RET 0, implicit %xmm0
+
+...
+---
+name:            test_add_double
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512F-NEXT:  - { id: 0, class: fr64 }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr64 }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr64 }
+# AVX512ALL-NEXT:  - { id: 0, class: fr64x }
+# AVX512ALL-NEXT:  - { id: 1, class: fr64x }
+# AVX512ALL-NEXT:  - { id: 2, class: fr64x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %xmm0
+# ALL-NEXT:     %1 = COPY %xmm1
+# SSE-NEXT:     %2 = ADDSDrr %0, %1
+# AVX-NEXT:     %2 = VADDSDrr %0, %1
+# AVX512F-NEXT: %2 = VADDSDZrr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(s64) = COPY %xmm0
+    %1(s64) = COPY %xmm1
+    %2(s64) = G_FADD %0, %1
+    %xmm0 = COPY %2(s64)
+    RET 0, implicit %xmm0
+
+...
+---
+name:            test_add_v4i32
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:           %0 = COPY %xmm0
+# ALL-NEXT:      %1 = COPY %xmm1
+# SSE-NEXT:      %2 = PADDDrr %0, %1
+# AVX-NEXT:      %2 = VPADDDrr %0, %1
+# AVX512F-NEXT:  %2 = VPADDDrr %0, %1
+# AVX512VL-NEXT: %2 = VPADDDZ128rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(<4 x s32>) = COPY %xmm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<4 x s32>) = G_ADD %0, %1
+    %xmm0 = COPY %2(<4 x s32>)
+    RET 0, implicit %xmm0
+
+...
+---
+name:            test_add_v4f32
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:           %0 = COPY %xmm0
+# ALL-NEXT:      %1 = COPY %xmm1
+# SSE-NEXT:      %2 = ADDPSrr %0, %1
+# AVX-NEXT:      %2 = VADDPSrr %0, %1
+# AVX512F-NEXT:  %2 = VADDPSrr %0, %1
+# AVX512VL-NEXT: %2 = VADDPSZ128rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(<4 x s32>) = COPY %xmm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<4 x s32>) = G_FADD %0, %1
+    %xmm0 = COPY %2(<4 x s32>)
+    RET 0, implicit %xmm0
+
+...

diff --git a/test/CodeGen/X86/GlobalISel/frameIndex-instructionselect.mir b/test/CodeGen/X86/GlobalISel/select-frameIndex.mir
similarity index 100%
rename from test/CodeGen/X86/GlobalISel/frameIndex-instructionselect.mir
rename to test/CodeGen/X86/GlobalISel/select-frameIndex.mir

diff --git a/test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir b/test/CodeGen/X86/GlobalISel/select-memop.mir
similarity index 59%
rename from test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir
rename to test/CodeGen/X86/GlobalISel/select-memop.mir
index 17522c3cb45ebd8f929b124a866f3d724e9d7c1a..943c9aceb4d19546687b22230e5afc2167413fc7 100644 (file)
--- a/test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir
+++ b/test/CodeGen/X86/GlobalISel/select-memop.mir
@@ -4,67 +4,7 @@
 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
 
 --- |
-  define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
-    %ret = add i64 %arg1, %arg2
-    ret i64 %ret
-  }
-
-  define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
-    %ret = add i32 %arg1, %arg2
-    ret i32 %ret
-  }
-
-  define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
-    %ret = sub i64 %arg1, %arg2
-    ret i64 %ret
-  }
-
-  define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
-    %ret = sub i32 %arg1, %arg2
-    ret i32 %ret
-  }
-
-  define float @test_add_float(float %arg1, float %arg2) {
-    %ret = fadd float %arg1, %arg2
-    ret float %ret
-  }
-
-  define double @test_add_double(double %arg1, double %arg2) {
-    %ret = fadd double %arg1, %arg2
-    ret double %ret
-  }
-
-  define float @test_sub_float(float %arg1, float %arg2) {
-    %ret = fsub float %arg1, %arg2
-    ret float %ret
-  }
-
-  define double @test_sub_double(double %arg1, double %arg2) {
-    %ret = fsub double %arg1, %arg2
-    ret double %ret
-  }
-
-  define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
-    %ret = add <4 x i32> %arg1, %arg2
-    ret <4 x i32> %ret
-  }
-
-  define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
-    %ret = sub <4 x i32> %arg1, %arg2
-    ret <4 x i32> %ret
-  }
-
-  define <4 x float>  @test_add_v4f32(<4 x float> %arg1, <4 x float>  %arg2) {
-    %ret = fadd <4 x float>  %arg1, %arg2
-    ret <4 x float>  %ret
-  }
-
-  define <4 x float>  @test_sub_v4f32(<4 x float> %arg1, <4 x float>  %arg2) {
-    %ret = fsub <4 x float>  %arg1, %arg2
-    ret <4 x float>  %ret
-  }
-  
-    define i8 @test_load_i8(i8* %p1) {
+  define i8 @test_load_i8(i8* %p1) {
     %r = load i8, i8* %p1
     ret i8 %r
   }
@@ -88,12 +28,12 @@
     %r = load float, float* %p1
     ret float %r
   }
-  
+
   define float @test_load_float_vecreg(float* %p1) {
     %r = load float, float* %p1
     ret float %r
   }
-  
+
 
   define double @test_load_double(double* %p1) {
     %r = load double, double* %p1
@@ -139,7 +79,7 @@
     store double %val, double* %p1
     ret double* %p1
   }
-  
+
   define double* @test_store_double_vec(double %val, double* %p1) {
     store double %val, double* %p1
     ret double* %p1
@@ -155,386 +95,6 @@
     ret <4 x i32>* %p1
   }
 
-...
-
----
-name:            test_add_i64
-legalized:       true
-regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64 }
-# ALL-NEXT:  - { id: 1, class: gr64 }
-# ALL-NEXT:  - { id: 2, class: gr64 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-# ALL:      %0 = COPY %rdi
-# ALL-NEXT: %1 = COPY %rsi
-# ALL-NEXT: %2 = ADD64rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %edi, %esi
-
-    %0(s64) = COPY %rdi
-    %1(s64) = COPY %rsi
-    %2(s64) = G_ADD %0, %1
-    %rax = COPY %2(s64)
-
-...
-
----
-name:            test_add_i32
-legalized:       true
-regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32 }
-# ALL-NEXT:  - { id: 1, class: gr32 }
-# ALL-NEXT:  - { id: 2, class: gr32 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-# ALL:      %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %esi
-# ALL-NEXT: %2 = ADD32rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %edi, %esi
-
-    %0(s32) = COPY %edi
-    %1(s32) = COPY %esi
-    %2(s32) = G_ADD %0, %1
-    %rax = COPY %2(s32)
-
-...
-
----
-name:            test_sub_i64
-legalized:       true
-regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64 }
-# ALL-NEXT:  - { id: 1, class: gr64 }
-# ALL-NEXT:  - { id: 2, class: gr64 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-# ALL:      %0 = COPY %rdi
-# ALL-NEXT: %1 = COPY %rsi
-# ALL-NEXT: %2 = SUB64rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %edi, %esi
-
-    %0(s64) = COPY %rdi
-    %1(s64) = COPY %rsi
-    %2(s64) = G_SUB %0, %1
-    %rax = COPY %2(s64)
-
-...
-
----
-name:            test_sub_i32
-legalized:       true
-regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32 }
-# ALL-NEXT:  - { id: 1, class: gr32 }
-# ALL-NEXT:  - { id: 2, class: gr32 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-# ALL:      %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %esi
-# ALL-NEXT: %2 = SUB32rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %edi, %esi
-
-    %0(s32) = COPY %edi
-    %1(s32) = COPY %esi
-    %2(s32) = G_SUB %0, %1
-    %rax = COPY %2(s32)
-
-...
-
----
-name:            test_add_float
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr32 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr32x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:          %0 = COPY %xmm0
-# ALL-NEXT:     %1 = COPY %xmm1
-# SSE-NEXT:     %2 = ADDSSrr %0, %1
-# AVX-NEXT:     %2 = VADDSSrr %0, %1
-# AVX512F-NEXT: %2 = VADDSSZrr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(s32) = COPY %xmm0
-    %1(s32) = COPY %xmm1
-    %2(s32) = G_FADD %0, %1
-    %xmm0 = COPY %2(s32)
-    RET 0, implicit %xmm0
-
-...
----
-name:            test_add_double
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr64 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr64x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:          %0 = COPY %xmm0
-# ALL-NEXT:     %1 = COPY %xmm1
-# SSE-NEXT:     %2 = ADDSDrr %0, %1
-# AVX-NEXT:     %2 = VADDSDrr %0, %1
-# AVX512F-NEXT: %2 = VADDSDZrr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(s64) = COPY %xmm0
-    %1(s64) = COPY %xmm1
-    %2(s64) = G_FADD %0, %1
-    %xmm0 = COPY %2(s64)
-    RET 0, implicit %xmm0
-
-...
----
-name:            test_sub_float
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr32 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr32x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:          %0 = COPY %xmm0
-# ALL-NEXT:     %1 = COPY %xmm1
-# SSE-NEXT:     %2 = SUBSSrr %0, %1
-# AVX-NEXT:     %2 = VSUBSSrr %0, %1
-# AVX512F-NEXT: %2 = VSUBSSZrr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(s32) = COPY %xmm0
-    %1(s32) = COPY %xmm1
-    %2(s32) = G_FSUB %0, %1
-    %xmm0 = COPY %2(s32)
-    RET 0, implicit %xmm0
-
-...
----
-name:            test_sub_double
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr64 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr64x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:          %0 = COPY %xmm0
-# ALL-NEXT:     %1 = COPY %xmm1
-# SSE-NEXT:     %2 = SUBSDrr %0, %1
-# AVX-NEXT:     %2 = VSUBSDrr %0, %1
-# AVX512F-NEXT: %2 = VSUBSDZrr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(s64) = COPY %xmm0
-    %1(s64) = COPY %xmm1
-    %2(s64) = G_FSUB %0, %1
-    %xmm0 = COPY %2(s64)
-    RET 0, implicit %xmm0
-...
----
-name:            test_add_v4i32
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = PADDDrr %0, %1
-# AVX-NEXT:      %2 = VPADDDrr %0, %1
-# AVX512F-NEXT:  %2 = VPADDDrr %0, %1
-# AVX512VL-NEXT: %2 = VPADDDZ128rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(<4 x s32>) = COPY %xmm0
-    %1(<4 x s32>) = COPY %xmm1
-    %2(<4 x s32>) = G_ADD %0, %1
-    %xmm0 = COPY %2(<4 x s32>)
-    RET 0, implicit %xmm0
-
-...
----
-name:            test_sub_v4i32
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = PSUBDrr %0, %1
-# AVX-NEXT:      %2 = VPSUBDrr %0, %1
-# AVX512F-NEXT:  %2 = VPSUBDrr %0, %1
-# AVX512VL-NEXT: %2 = VPSUBDZ128rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(<4 x s32>) = COPY %xmm0
-    %1(<4 x s32>) = COPY %xmm1
-    %2(<4 x s32>) = G_SUB %0, %1
-    %xmm0 = COPY %2(<4 x s32>)
-    RET 0, implicit %xmm0
-
-...
----
-name:            test_add_v4f32
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = ADDPSrr %0, %1
-# AVX-NEXT:      %2 = VADDPSrr %0, %1
-# AVX512F-NEXT:  %2 = VADDPSrr %0, %1
-# AVX512VL-NEXT: %2 = VADDPSZ128rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(<4 x s32>) = COPY %xmm0
-    %1(<4 x s32>) = COPY %xmm1
-    %2(<4 x s32>) = G_FADD %0, %1
-    %xmm0 = COPY %2(<4 x s32>)
-    RET 0, implicit %xmm0
-
-...
----
-name:            test_sub_v4f32
-alignment:       4
-legalized:       true
-regBankSelected: true
-selected:        false
-tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
-registers:
-  - { id: 0, class: vecr }
-  - { id: 1, class: vecr }
-  - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = SUBPSrr %0, %1
-# AVX-NEXT:      %2 = VSUBPSrr %0, %1
-# AVX512F-NEXT:  %2 = VSUBPSrr %0, %1
-# AVX512VL-NEXT: %2 = VSUBPSZ128rr %0, %1
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: %xmm0, %xmm1
-
-    %0(<4 x s32>) = COPY %xmm0
-    %1(<4 x s32>) = COPY %xmm1
-    %2(<4 x s32>) = G_FSUB %0, %1
-    %xmm0 = COPY %2(<4 x s32>)
-    RET 0, implicit %xmm0
-
 ...
 ---
 # ALL-LABEL: name:            test_load_i8

diff --git a/test/CodeGen/X86/GlobalISel/select-sub.mir b/test/CodeGen/X86/GlobalISel/select-sub.mir
new file mode 100644 (file)
index 0000000..d4db6ee
--- /dev/null
+++ b/test/CodeGen/X86/GlobalISel/select-sub.mir
@@ -0,0 +1,225 @@
+# RUN: llc -mtriple=x86_64-linux-gnu                                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx                      -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+
+--- |
+  define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
+    %ret = sub i64 %arg1, %arg2
+    ret i64 %ret
+  }
+
+  define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
+    %ret = sub i32 %arg1, %arg2
+    ret i32 %ret
+  }
+
+  define float @test_sub_float(float %arg1, float %arg2) {
+    %ret = fsub float %arg1, %arg2
+    ret float %ret
+  }
+
+  define double @test_sub_double(double %arg1, double %arg2) {
+    %ret = fsub double %arg1, %arg2
+    ret double %ret
+  }
+
+  define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
+    %ret = sub <4 x i32> %arg1, %arg2
+    ret <4 x i32> %ret
+  }
+
+  define <4 x float>  @test_sub_v4f32(<4 x float> %arg1, <4 x float>  %arg2) {
+    %ret = fsub <4 x float>  %arg1, %arg2
+    ret <4 x float>  %ret
+  }
+
+...
+---
+name:            test_sub_i64
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:  - { id: 0, class: gr64 }
+# ALL-NEXT:  - { id: 1, class: gr64 }
+# ALL-NEXT:  - { id: 2, class: gr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:      %0 = COPY %rdi
+# ALL-NEXT: %1 = COPY %rsi
+# ALL-NEXT: %2 = SUB64rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi, %esi
+
+    %0(s64) = COPY %rdi
+    %1(s64) = COPY %rsi
+    %2(s64) = G_SUB %0, %1
+    %rax = COPY %2(s64)
+
+...
+
+---
+name:            test_sub_i32
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:  - { id: 0, class: gr32 }
+# ALL-NEXT:  - { id: 1, class: gr32 }
+# ALL-NEXT:  - { id: 2, class: gr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:      %0 = COPY %edi
+# ALL-NEXT: %1 = COPY %esi
+# ALL-NEXT: %2 = SUB32rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi, %esi
+
+    %0(s32) = COPY %edi
+    %1(s32) = COPY %esi
+    %2(s32) = G_SUB %0, %1
+    %rax = COPY %2(s32)
+
+...
+---
+name:            test_sub_float
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512F-NEXT:  - { id: 0, class: fr32 }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr32 }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr32 }
+# AVX512ALL-NEXT:  - { id: 0, class: fr32x }
+# AVX512ALL-NEXT:  - { id: 1, class: fr32x }
+# AVX512ALL-NEXT:  - { id: 2, class: fr32x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %xmm0
+# ALL-NEXT:     %1 = COPY %xmm1
+# SSE-NEXT:     %2 = SUBSSrr %0, %1
+# AVX-NEXT:     %2 = VSUBSSrr %0, %1
+# AVX512F-NEXT: %2 = VSUBSSZrr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(s32) = COPY %xmm0
+    %1(s32) = COPY %xmm1
+    %2(s32) = G_FSUB %0, %1
+    %xmm0 = COPY %2(s32)
+    RET 0, implicit %xmm0
+
+...
+---
+name:            test_sub_double
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512F-NEXT:  - { id: 0, class: fr64 }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr64 }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr64 }
+# AVX512ALL-NEXT:  - { id: 0, class: fr64x }
+# AVX512ALL-NEXT:  - { id: 1, class: fr64x }
+# AVX512ALL-NEXT:  - { id: 2, class: fr64x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %xmm0
+# ALL-NEXT:     %1 = COPY %xmm1
+# SSE-NEXT:     %2 = SUBSDrr %0, %1
+# AVX-NEXT:     %2 = VSUBSDrr %0, %1
+# AVX512F-NEXT: %2 = VSUBSDZrr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(s64) = COPY %xmm0
+    %1(s64) = COPY %xmm1
+    %2(s64) = G_FSUB %0, %1
+    %xmm0 = COPY %2(s64)
+    RET 0, implicit %xmm0
+...
+---
+name:            test_sub_v4i32
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:           %0 = COPY %xmm0
+# ALL-NEXT:      %1 = COPY %xmm1
+# SSE-NEXT:      %2 = PSUBDrr %0, %1
+# AVX-NEXT:      %2 = VPSUBDrr %0, %1
+# AVX512F-NEXT:  %2 = VPSUBDrr %0, %1
+# AVX512VL-NEXT: %2 = VPSUBDZ128rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(<4 x s32>) = COPY %xmm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<4 x s32>) = G_SUB %0, %1
+    %xmm0 = COPY %2(<4 x s32>)
+    RET 0, implicit %xmm0
+
+...
+---
+name:            test_sub_v4f32
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+# ALL: registers:
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:           %0 = COPY %xmm0
+# ALL-NEXT:      %1 = COPY %xmm1
+# SSE-NEXT:      %2 = SUBPSrr %0, %1
+# AVX-NEXT:      %2 = VSUBPSrr %0, %1
+# AVX512F-NEXT:  %2 = VSUBPSrr %0, %1
+# AVX512VL-NEXT: %2 = VSUBPSZ128rr %0, %1
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %xmm0, %xmm1
+
+    %0(<4 x s32>) = COPY %xmm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<4 x s32>) = G_FSUB %0, %1
+    %xmm0 = COPY %2(<4 x s32>)
+    RET 0, implicit %xmm0
+
+...