AMDGPU: Fix isTypeDesirableForOp for i16

This should do nothing for targets without i16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289235 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp
index eeab4821e50dac45d6ba89276160c0a21c2555ad..0c35c2757a1f0705aaa71f1cd2c19fcc6ee103f9 100644 (file)
--- a/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -658,10 +658,22 @@ bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
 }
 
 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
-
-  // i16 is not desirable unless it is a load or a store.
-  if (VT == MVT::i16 && Op != ISD::LOAD && Op != ISD::STORE)
-    return false;
+  if (Subtarget->has16BitInsts() && VT == MVT::i16) {
+    switch (Op) {
+    case ISD::LOAD:
+    case ISD::STORE:
+
+    // These operations are done with 32-bit instructions anyway.
+    case ISD::AND:
+    case ISD::OR:
+    case ISD::XOR:
+    case ISD::SELECT:
+      // TODO: Extensions?
+      return true;
+    default:
+      return false;
+    }
+  }
 
   // SimplifySetCC uses this function to determine whether or not it should
   // create setcc with i1 operands.  We don't have instructions for i1 setcc.