SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
- APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+ APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
#endif
- while(1) {
+ while (1) {
if (esp_cpu_in_ocd_debug_mode()) {
__asm__ ("break 0,0");
}
- *((int*) 0) = 0;
+ *((int *) 0) = 0;
}
}
int debugRsn;
asm("rsr.debugcause %0":"=r"(debugRsn));
panicPutStr("Debug exception reason: ");
- if (debugRsn&XCHAL_DEBUGCAUSE_ICOUNT_MASK) panicPutStr("SingleStep ");
- if (debugRsn&XCHAL_DEBUGCAUSE_IBREAK_MASK) panicPutStr("HwBreakpoint ");
- if (debugRsn&XCHAL_DEBUGCAUSE_DBREAK_MASK) {
+ if (debugRsn & XCHAL_DEBUGCAUSE_ICOUNT_MASK) {
+ panicPutStr("SingleStep ");
+ }
+ if (debugRsn & XCHAL_DEBUGCAUSE_IBREAK_MASK) {
+ panicPutStr("HwBreakpoint ");
+ }
+ if (debugRsn & XCHAL_DEBUGCAUSE_DBREAK_MASK) {
//Unlike what the ISA manual says, this core seemingly distinguishes from a DBREAK
//reason caused by watchdog 0 and one caused by watchdog 1 by setting bit 8 of the
//debugcause if the cause is watchdog 1 and clearing it if it's watchdog 0.
- if (debugRsn&(1<<8)) {
+ if (debugRsn & (1 << 8)) {
#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
const char *name = pcTaskGetTaskName(xTaskGetCurrentTaskHandleForCPU(core_id));
panicPutStr("Stack canary watchpoint triggered (");
} else {
panicPutStr("Watchpoint 0 triggered ");
}
- }
- if (debugRsn&XCHAL_DEBUGCAUSE_BREAK_MASK) panicPutStr("BREAK instr ");
- if (debugRsn&XCHAL_DEBUGCAUSE_BREAKN_MASK) panicPutStr("BREAKN instr ");
- if (debugRsn&XCHAL_DEBUGCAUSE_DEBUGINT_MASK) panicPutStr("DebugIntr ");
+ }
+ if (debugRsn & XCHAL_DEBUGCAUSE_BREAK_MASK) {
+ panicPutStr("BREAK instr ");
+ }
+ if (debugRsn & XCHAL_DEBUGCAUSE_BREAKN_MASK) {
+ panicPutStr("BREAKN instr ");
+ }
+ if (debugRsn & XCHAL_DEBUGCAUSE_DEBUGINT_MASK) {
+ panicPutStr("DebugIntr ");
+ }
panicPutStr("\r\n");
}
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
- APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+ APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
#endif
setFirstBreakpoint(frame->pc);
haltOtherCore();
esp_dport_access_int_abort();
if (!abort_called) {
- panicPutStr("Guru Meditation Error of type ");
+ panicPutStr("Guru Meditation Error: Core ");
+ panicPutDec(xPortGetCoreID());
+ panicPutStr(" panic'ed (");
int exccause = frame->exccause;
if (exccause < NUM_EDESCS) {
panicPutStr(edesc[exccause]);
} else {
panicPutStr("Unknown");
}
- panicPutStr(" occurred on core ");
- panicPutDec(xPortGetCoreID());
+ panicPutStr(")\r\n");
if (esp_cpu_in_ocd_debug_mode()) {
panicPutStr(" at pc=");
panicPutHex(frame->pc);
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
- APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+ APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
#endif
//Stick a hardware breakpoint on the address the handler returns to. This way, the OCD debugger
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#else
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
- APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+ APPTRACE_ONPANIC_HOST_FLUSH_TMO);
#endif
reconfigureAllWdts();
#endif
esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags)
{
int x;
- if (no<0 || no>1) return ESP_ERR_INVALID_ARG;
- if (flags&(~0xC0000000)) return ESP_ERR_INVALID_ARG;
- int dbreakc=0x3F;
+ if (no < 0 || no > 1) {
+ return ESP_ERR_INVALID_ARG;
+ }
+ if (flags & (~0xC0000000)) {
+ return ESP_ERR_INVALID_ARG;
+ }
+ int dbreakc = 0x3F;
//We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
- for (x=0; x<7; x++) {
- if (size==(1<<x)) break;
- dbreakc<<=1;
+ for (x = 0; x < 7; x++) {
+ if (size == (1 << x)) {
+ break;
+ }
+ dbreakc <<= 1;
+ }
+ if (x == 7) {
+ return ESP_ERR_INVALID_ARG;
}
- if (x==7) return ESP_ERR_INVALID_ARG;
//Mask mask and add in flags.
- dbreakc=(dbreakc&0x3f)|flags;
+ dbreakc = (dbreakc & 0x3f) | flags;
- if (no==0) {
+ if (no == 0) {
asm volatile(
"wsr.dbreaka0 %0\n" \
"wsr.dbreakc0 %1\n" \
- ::"r"(adr),"r"(dbreakc));
+ ::"r"(adr), "r"(dbreakc));
} else {
asm volatile(
"wsr.dbreaka1 %0\n" \
"wsr.dbreakc1 %1\n" \
- ::"r"(adr),"r"(dbreakc));
+ ::"r"(adr), "r"(dbreakc));
}
return ESP_OK;
}
void esp_clear_watchpoint(int no)
{
//Setting a dbreakc register to 0 makes it trigger on neither load nor store, effectively disabling it.
- int dbreakc=0;
- if (no==0) {
+ int dbreakc = 0;
+ if (no == 0) {
asm volatile(
"wsr.dbreakc0 %0\n" \
::"r"(dbreakc));
--- /dev/null
+#include "unity.h"
+#include "esp_system.h"
+#include "string.h"
+
+
+TEST_CASE("make exception", "[restart][reset=StoreProhibited,SW_CPU_RESET]")
+{
+ *(int *) NULL = 0;
+}
#include "freertos/task.h"
-TEST_CASE("restart from PRO CPU", "[restart][ignore]")
+TEST_CASE("restart from PRO CPU", "[restart][reset=SW_CPU_RESET]")
{
esp_restart();
}
-static void restart_task(void* arg)
+static void restart_task(void *arg)
{
esp_restart();
}
-TEST_CASE("restart from APP CPU", "[restart][ignore]")
+TEST_CASE("restart from APP CPU", "[restart][reset=SW_CPU_RESET]")
{
xTaskCreatePinnedToCore(&restart_task, "restart", 2048, NULL, 5, NULL, 1);
-
- while(true) {
+ while (true) {
;
}
}
-
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
-TEST_CASE("esp_deepsleep works", "[deepsleep][ignore]")
+TEST_CASE("esp_deepsleep works", "[deepsleep][reset=DEEPSLEEP_RESET]")
{
esp_deep_sleep(2000000);
}
-static void deep_sleep_task(void* arg)
+static void deep_sleep_task(void *arg)
{
esp_deep_sleep_start();
}
// keep running some non-IRAM code
vTaskSuspendAll();
- while(true) {
+
+ while (true) {
;
}
}
-TEST_CASE("wake up from deep sleep using timer", "[deepsleep][ignore]")
+TEST_CASE("wake up using timer", "[deepsleep][reset=DEEPSLEEP_RESET]")
{
esp_sleep_enable_timer_wakeup(2000000);
esp_deep_sleep_start();
}
+
TEST_CASE("wake up from light sleep using timer", "[deepsleep]")
{
esp_sleep_enable_timer_wakeup(2000000);
esp_light_sleep_start();
gettimeofday(&tv_stop, NULL);
float dt = (tv_stop.tv_sec - tv_start.tv_sec) * 1e3f +
- (tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
+ (tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt);
}
-TEST_CASE("enter deep sleep on APP CPU and wake up using timer", "[deepsleep][ignore]")
+TEST_CASE("enter deep sleep on APP CPU and wake up using timer", "[deepsleep][reset=DEEPSLEEP_RESET]")
{
esp_sleep_enable_timer_wakeup(2000000);
do_deep_sleep_from_app_cpu();
+# -*- coding: utf-8 -*-
import re
import time
from TCAction import TCActionBase
from NativeLog import NativeLog
+
class UnitTest(PerformanceTCBase.PerformanceTCBase):
- def __init__(self, name, test_env, cmd_set, timeout=30, log_path=TCActionBase.LOG_PATH):
- PerformanceTCBase.PerformanceTCBase.__init__(self, name, test_env, cmd_set=cmd_set,
+ def __init__(self, test_case, test_env, cmd_set, timeout=30, log_path=TCActionBase.LOG_PATH):
+ PerformanceTCBase.PerformanceTCBase.__init__(self, test_case, test_env, cmd_set=cmd_set,
timeout=timeout, log_path=log_path)
-
- self.test_case = None
+ self.case = cmd_set[1][0]
self.test_timeout = 20
-
- # load param from excel
- for i in range(1, len(cmd_set)):
- if cmd_set[i][0] != "dummy":
- cmd_string = "self.test_case = " + "\"" + cmd_set[i][0] + "\""
- exec cmd_string
+ self.reset_reason = test_case['reset']
self.result_cntx = TCActionBase.ResultCheckContext(self, test_env, self.tc_name)
- pass
def send_commands(self):
self.flush_data("UT1")
-
try:
- self.serial_write_line("UT1", "\"" + self.test_case + "\"")
+ self.serial_write_line("UT1", "\"" + self.case + "\"")
data = ""
+
for _ in range(self.timeout):
- time.sleep(1) #wait for test to run before reading result
+ time.sleep(1) # wait for test to run before reading result
data += self.serial_read_data("UT1")
- if re.search('[^0].* Tests 0 F', data): #check that number of tests run != 0 and number of tests failed == 0
+ if re.search('[^0].* Tests 0 F',
+ data): # check that number of tests run != 0 and number of tests failed == 0
self.set_result("Succeed")
break
else:
self.set_result("Fail")
- except StandardError,e:
+ reset_list = self.reset_reason.split(",") if self.reset_reason else ''
+ pattern = re.compile(r"(ets [\w]{3} [\d]{1,2} [\d]{4} [\d]{2}:[\d]{2}:[\d]{2}[^(\)]*\([\w].*?\))"
+ r"|(Guru Meditation Error: Core [\d] panic'ed \([\w].*?\))")
+ reset_exception = pattern.findall(data)
+ if reset_list and len(reset_list) == len(reset_exception):
+ for i, reset in enumerate(reset_list):
+ temp_reset = reset_exception[i]
+ if reset not in "".join(temp_reset):
+ self.set_result("Fail")
+ break
+ else:
+ self.set_result("Succeed")
+
+ except StandardError, e:
NativeLog.add_exception_log(e)
def execute(self):
TCActionBase.TCActionBase.execute(self)
self.send_commands()
+
def main():
pass
+
if __name__ == '__main__':
pass
test_env:
default: "UT_T1_1"
omitted: "UT_T1_1"
+reset:
+ default: "POWERON_RESET"
+ omitted: " "
\ No newline at end of file
"test point 1": "basic function",
"version": "v1 (2016-12-06)",
"test environment": "UT_T1_1",
+ "reset": "",
"expected result": "1. set succeed"
}
"test point 2": prop["module"],
"steps": name,
"test environment": prop["test_env"],
+ "reset": prop["reset"],
"sub module": self.module_map[prop["module"]]['sub module'],
"summary": name})
return test_case
projects / esp-idf / commitdiff