[AArch64][WinCFI] Do not pair callee-save instructions in LoadStoreOptimizer

Prevent the LoadStoreOptimizer from pairing any load/store instructions with
instructions from the prologue/epilogue if the CFI information has encoded the
operations as separate instructions.  This would otherwise lead to a mismatch
of the actual prologue size from the size as recorded in the Windows CFI.

Reviewers: efriedma, mstorsjo, ssijaric

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D65817

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368164 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index e54d365fdaec437fa10e60b9ff4fce3fb2c687e4..19061c5fc0914395f00e20e5e6d66ad965d399f3 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -32,6 +32,7 @@
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/GlobalValue.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/Casting.h"
@@ -1928,6 +1929,17 @@ bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
   if (isLdStPairSuppressed(MI))
     return false;
 
+  // Do not pair any callee-save store/reload instructions in the
+  // prologue/epilogue if the CFI information encoded the operations as separate
+  // instructions, as that will cause the size of the actual prologue to mismatch
+  // with the prologue size recorded in the Windows CFI.
+  const MCAsmInfo *MAI = MI.getMF()->getTarget().getMCAsmInfo();
+  bool NeedsWinCFI = MAI->usesWindowsCFI() &&
+                     MI.getMF()->getFunction().needsUnwindTableEntry();
+  if (NeedsWinCFI && (MI.getFlag(MachineInstr::FrameSetup) ||
+                      MI.getFlag(MachineInstr::FrameDestroy)))
+    return false;
+
   // On some CPUs quad load/store pairs are slower than two single load/stores.
   if (Subtarget.isPaired128Slow()) {
     switch (MI.getOpcode()) {

diff --git a/test/CodeGen/AArch64/wineh1.mir b/test/CodeGen/AArch64/wineh1.mir
index b01d4cb529c19798f76a4ab938f3c16902e42256..1ffaa25d30d8e76801d00d47b32e8a333417f5c5 100644 (file)
--- a/test/CodeGen/AArch64/wineh1.mir
+++ b/test/CodeGen/AArch64/wineh1.mir
@@ -1,5 +1,7 @@
 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj  \
 # RUN:   | llvm-readobj --unwind | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -run-pass=aarch64-ldst-opt \
+# RUN:   | FileCheck %s --check-prefix=CHECK-LDSTOPT
 # This test case checks the basic validity of the .xdata section.  It's
 # documented at:
 # https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
@@ -7,7 +9,7 @@
 # We expect to see the following in the .xdata section:
 
 # CHECK:        ExceptionData {
-# CHECK-NEXT:      FunctionLength: 92
+# CHECK-NEXT:      FunctionLength: 96
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No
@@ -24,7 +26,7 @@
 # CHECK-NEXT:      ]
 # CHECK-NEXT:      EpilogueScopes [
 # CHECK-NEXT:        EpilogueScope {
-# CHECK-NEXT:          StartOffset: 15
+# CHECK-NEXT:          StartOffset: 16
 # CHECK-NEXT:          EpilogueStartIndex: 13
 # CHECK-NEXT:          Opcodes [
 # CHECK-NEXT:            0xc808              ; ldp x19, x20, [sp, #64]
@@ -39,6 +41,12 @@
 # CHECK-NEXT:        }
 # CHECK-NEXT:      ]
 # CHECK-NEXT:    }
+
+# Check that the load-store optimizer does not merge the two
+# callee-saved stores in the prologue.
+# CHECK-LDSTOPT: name: test
+# CHECK-LDSTOPT: frame-setup STRXui killed $x21, $sp, 6
+# CHECK-LDSTOPT: frame-setup STRXui killed $x22, $sp, 7
 ...
 ---
 name:            test

diff --git a/test/CodeGen/AArch64/wineh2.mir b/test/CodeGen/AArch64/wineh2.mir
index 9352181c473f760d347c0268398115f3d67157dc..05a232f753f394558129d87ba24d6673248afbd8 100644 (file)
--- a/test/CodeGen/AArch64/wineh2.mir
+++ b/test/CodeGen/AArch64/wineh2.mir
@@ -3,7 +3,7 @@
 # Test that the pre/post increment save of a flating point register is correct.
 
 # CHECK:        ExceptionData {
-# CHECK-NEXT:      FunctionLength: 136
+# CHECK-NEXT:      FunctionLength: 144
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No
@@ -23,7 +23,7 @@
 # CHECK-NEXT:      ]
 # CHECK-NEXT:      EpilogueScopes [
 # CHECK-NEXT:        EpilogueScope {
-# CHECK-NEXT:          StartOffset: 25
+# CHECK-NEXT:          StartOffset: 26
 # CHECK-NEXT:          EpilogueStartIndex: 19
 # CHECK-NEXT:          Opcodes [
 # CHECK-NEXT:            0xc80e              ; ldp x19, x20, [sp, #112]

diff --git a/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll b/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll
index daa7da201d5351c212d6087fa10034633ee7965f..c02eea5da504110ba3410e733502e90e060c87ea 100644 (file)
--- a/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll
+++ b/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll
@@ -28,9 +28,9 @@
 ; OBJ:     OffsetInParent: 0
 ; OBJ:     BasePointerOffset: 12
 ; OBJ:     LocalVariableAddrRange {
-; OBJ:       OffsetStart: .text+0x10
+; OBJ:       OffsetStart: .text+0x14
 ; OBJ:       ISectStart: 0x0
-; OBJ:       Range: 0x2C
+; OBJ:       Range: 0x30
 ; OBJ:     }
 ; OBJ:   }